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Searched refs:vaddr0 (Results 1 – 10 of 10) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dds-combine-with-dependence.ll17 %vaddr0 = bitcast float addrspace(3)* %tmp0 to <3 x float> addrspace(3)*
18 %load0 = load <3 x float>, <3 x float> addrspace(3)* %vaddr0, align 4
49 %vaddr0 = bitcast float addrspace(3)* %tmp0 to <3 x float> addrspace(3)*
50 %load0 = load <3 x float>, <3 x float> addrspace(3)* %vaddr0, align 4
83 %vaddr0 = bitcast float addrspace(3)* %tmp0 to <3 x float> addrspace(3)*
84 %load0 = load <3 x float>, <3 x float> addrspace(3)* %vaddr0, align 4
116 %vaddr0 = bitcast float addrspace(3)* %tmp0 to <3 x float> addrspace(3)*
117 %load0 = load <3 x float>, <3 x float> addrspace(3)* %vaddr0, align 4
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DSIMCCodeEmitter.cpp351 int vaddr0 = AMDGPU::getNamedOperandIdx(MI.getOpcode(), in encodeInstruction() local
352 AMDGPU::OpName::vaddr0); in encodeInstruction()
355 assert(vaddr0 >= 0 && srsrc > vaddr0); in encodeInstruction()
356 unsigned NumExtraAddrs = srsrc - vaddr0 - 1; in encodeInstruction()
360 getMachineOpValue(MI, MI.getOperand(vaddr0 + 1 + i), Encoding, Fixups, in encodeInstruction()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DMIMGInstructions.td372 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, DMask:$dmask,
397 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, DMask:$dmask,
541 let InOperandList = !con((ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc,
725 let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc,
755 let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc,
903 let AsmString = opcode#" $vdata, $vaddr0, $srsrc, $ssamp$dmask$dim$unorm"
930 let AsmString = opcode#" $vdata, $vaddr0, $srsrc, $ssamp$dmask$dim$unorm"
1144 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_128:$srsrc),
1146 let AsmString = opcode#" $vdata, $vaddr0, $srsrc"#!if(A16, "$a16", "");
1162 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_128:$srsrc),
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H A DSIInstrFormats.td356 bits<8> vaddr0;
367 let Inst{39-32} = vaddr0;
383 bits<8> vaddr0;
399 let Inst{39-32} = vaddr0;
H A DGCNNSAReassign.cpp176 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); in CheckNSA()
287 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::vaddr0); in runOnMachineFunction()
H A DSILoadStoreOptimizer.cpp398 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0) == -1) in getInstClass()
566 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0); in getRegs()
696 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0) + J; in setMI()
H A DSIShrinkInstructions.cpp257 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); in shrinkMIMG()
H A DSIInstrInfo.cpp403 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0); in getMemOperandsWithOffsetWidth()
4492 AMDGPU::OpName::vaddr0); in verifyInstruction()
7500 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0); in getInstSizeInBytes()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp650 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); in getInstruction()
842 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); in convertMIMGInst()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp3610 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0); in validateMIMGAddrSize()