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/llvm-project-15.0.7/llvm/test/tools/llvm-objdump/ELF/
H A Dprogram-headers.test7 # ELF32-NEXT: PHDR off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0
9 # ELF32-NEXT: PHDR off 0x00000317 vaddr 0x00002000 paddr 0x00002000 align 2**0
11 # ELF32-NEXT: UNKNOWN off 0x00000317 vaddr 0x00002000 paddr 0x00002000 align 2**0
13 # ELF32-NEXT: DYNAMIC off 0x00000324 vaddr 0x00006000 paddr 0x00006000 align 2**0
15 # ELF32-NEXT: INTERP off 0x0000031e vaddr 0x00003000 paddr 0x00003000 align 2**0
17 # ELF32-NEXT: NOTE off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0
19 # ELF32-NEXT: UNKNOWN off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0
21 # ELF32-NEXT: TLS off 0x00000322 vaddr 0x00004000 paddr 0x00004000 align 2**0
23 # ELF32-NEXT: UNKNOWN off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0
25 # ELF32-NEXT:EH_FRAME off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0
[all …]
H A Dprivate-headers.test7 # CHECK-NEXT: LOAD off 0x00000000000000b0 vaddr 0x0000000000001000 paddr 0x0000000000001000 alig…
9 # CHECK-NEXT: DYNAMIC off 0x00000000000000cd vaddr 0x000000000000101d paddr 0x000000000000101d alig…
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/ARM/
H A Dinsertelement.ll12 %T_i8v* %vaddr) {
13 %v0 = load %T_i8v, %T_i8v* %vaddr
17 store %T_i8v %v2, %T_i8v* %vaddr
26 %T_i16v* %vaddr) {
27 %v0 = load %T_i16v, %T_i16v* %vaddr
31 store %T_i16v %v2, %T_i16v* %vaddr
39 %T_i32v* %vaddr) {
40 %v0 = load %T_i32v, %T_i32v* %vaddr
44 store %T_i32v %v2, %T_i32v* %vaddr
/llvm-project-15.0.7/llvm/docs/AMDGPU/
H A DAMDGPUAsmGFX7.rst43 …ds_add_src2_u32 :ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>` …
44 …ds_add_src2_u64 :ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>` …
51 …ds_and_src2_b32 :ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>` …
52 …ds_and_src2_b64 :ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>` …
66 …ds_dec_src2_u32 :ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>` …
67 …ds_dec_src2_u64 :ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>` …
78 …ds_inc_src2_u32 :ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>` …
79 …ds_inc_src2_u64 :ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>` …
92 …ds_max_src2_f32 :ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>` …
93 …ds_max_src2_f64 :ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>` …
[all …]
H A Dgfx10_vaddr_9aeece.rst10 vaddr title
15 * Address = :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>` + :ref:`offset12s<amdgpu_synid_flat_offse…
16 …10_saddr_beaa25>` + :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>` + :ref:`offset12s<amdgpu_synid_f…
H A Dgfx908_vaddr_0212e3.rst10 vaddr title
15 * Address = :ref:`vaddr<amdgpu_synid_gfx908_vaddr_0212e3>` + :ref:`offset13s<amdgpu_synid_flat_offs…
16 …id_gfx908_saddr>` + :ref:`vaddr<amdgpu_synid_gfx908_vaddr_0212e3>` + :ref:`offset13s<amdgpu_synid_…
H A Dgfx1030_vaddr_9aeece.rst10 vaddr title
15 * Address = :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>` + :ref:`offset12s<amdgpu_synid_flat_off…
16 …0_saddr_beaa25>` + :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>` + :ref:`offset12s<amdgpu_synid_…
H A Dgfx9_vaddr_0212e3.rst10 vaddr title
15 * Address = :ref:`vaddr<amdgpu_synid_gfx9_vaddr_0212e3>` + :ref:`offset13s<amdgpu_synid_flat_offset…
16 …fx9_saddr_a37373>` + :ref:`vaddr<amdgpu_synid_gfx9_vaddr_0212e3>` + :ref:`offset13s<amdgpu_synid_f…
H A Dgfx940_vaddr_0212e3.rst10 vaddr title
15 * Address = :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>` + :ref:`offset13s<amdgpu_synid_flat_offs…
16 …40_saddr_a37373>` + :ref:`vaddr<amdgpu_synid_gfx940_vaddr_0212e3>` + :ref:`offset13s<amdgpu_synid_…
H A Dgfx90a_vaddr_0212e3.rst10 vaddr title
15 * Address = :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_0212e3>` + :ref:`offset13s<amdgpu_synid_flat_offs…
16 …0a_saddr_a37373>` + :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_0212e3>` + :ref:`offset13s<amdgpu_synid_…
H A DAMDGPUAsmGFX10.rst259 …ds_add_src2_f32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` …
260 …ds_add_src2_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` …
261 …ds_add_src2_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` …
268 …ds_and_src2_b32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` …
269 …ds_and_src2_b64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` …
284 …ds_dec_src2_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` …
285 …ds_dec_src2_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` …
296 …ds_inc_src2_u32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` …
297 …ds_inc_src2_u64 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` …
310 …ds_max_src2_f32 :ref:`vaddr<amdgpu_synid_gfx10_vaddr_f20ee4>` …
[all …]
H A DAMDGPUAsmGFX9.rst45 …ds_add_src2_f32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>` …
46 …ds_add_src2_u32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>` …
47 …ds_add_src2_u64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>` …
54 …ds_and_src2_b32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>` …
55 …ds_and_src2_b64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>` …
70 …ds_dec_src2_u32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>` …
71 …ds_dec_src2_u64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>` …
82 …ds_inc_src2_u32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>` …
83 …ds_inc_src2_u64 :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>` …
96 …ds_max_src2_f32 :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>` …
[all …]
H A DAMDGPUAsmGFX1030.rst328 …ds_ordered_count :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<am…
335 …ds_read_b128 :ref:`vdst<amdgpu_synid_gfx1030_vdst_69a144>`, :ref:`vaddr<am…
336 …ds_read_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<am…
337 …ds_read_b64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`vaddr<am…
338 …ds_read_b96 :ref:`vdst<amdgpu_synid_gfx1030_vdst_48e42f>`, :ref:`vaddr<am…
339 …ds_read_i16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<am…
340 …ds_read_i8 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<am…
341 …ds_read_i8_d16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<am…
342 …ds_read_i8_d16_hi :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<am…
556 …image_bvh64_intersect_ray :ref:`vdst<amdgpu_synid_gfx1030_vdst_f8490d>`, :ref:`vaddr<amdgpu_syni…
[all …]
H A DAMDGPUAsmGFX8.rst45 …ds_add_src2_f32 :ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>` …
46 …ds_add_src2_u32 :ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>` …
47 …ds_add_src2_u64 :ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>` …
54 …ds_and_src2_b32 :ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>` …
55 …ds_and_src2_b64 :ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>` …
70 …ds_dec_src2_u32 :ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>` …
71 …ds_dec_src2_u64 :ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>` …
82 …ds_inc_src2_u32 :ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>` …
83 …ds_inc_src2_u64 :ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>` …
96 …ds_max_src2_f32 :ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>` …
[all …]
H A DAMDGPUAsmGFX90a.rst41 …ds_add_f32 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`, :ref…
42 …ds_add_f64 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`, :ref…
47 …ds_add_u32 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`, :ref…
48 …ds_add_u64 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`, :ref…
49 …ds_and_b32 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`, :ref…
50 …ds_and_b64 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`, :ref…
67 …ds_dec_u32 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`, :ref…
68 …ds_dec_u64 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`, :ref…
77 …ds_inc_u32 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`, :ref…
78 …ds_inc_u64 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`, :ref…
[all …]
H A DAMDGPUAsmGFX940.rst41 …ds_add_f32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref…
42 …ds_add_f64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref…
47 …ds_add_u32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref…
48 …ds_add_u64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref…
49 …ds_and_b32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref…
50 …ds_and_b64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref…
67 …ds_dec_u32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref…
68 …ds_dec_u64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref…
77 …ds_inc_u32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref…
78 …ds_inc_u64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref…
[all …]
H A DAMDGPUAsmGFX1013.rst43 …image_bvh64_intersect_ray :ref:`vdst<amdgpu_synid_gfx1013_vdst_f8490d>`, :ref:`vaddr<amdgpu…
44 …image_bvh_intersect_ray :ref:`vdst<amdgpu_synid_gfx1013_vdst_f8490d>`, :ref:`vaddr<amdgpu…
45 …image_msaa_load :ref:`vdst<amdgpu_synid_gfx1013_vdst_473a69>`, :ref:`vaddr<amdgpu…
H A Dgfx940_vaddr_6ab80d.rst10 vaddr title
15 * Offset = [:ref:`vaddr<amdgpu_synid_gfx940_vaddr_6ab80d>`] + [:ref:`saddr<amdgpu_synid_gfx940_sadd…
H A Dgfx1030_vaddr_373b95.rst10 vaddr title
15 * Offset = [:ref:`vaddr<amdgpu_synid_gfx1030_vaddr_373b95>`] + [:ref:`saddr<amdgpu_synid_gfx1030_sa…
/llvm-project-15.0.7/llvm/test/Object/
H A Dobjdump-private-headers.test9 ELF-i386: LOAD off 0x00000000 vaddr 0x08048000 paddr 0x08048000 align 2**12
11 ELF-i386: STACK off 0x00000000 vaddr 0x00000000 paddr 0x00000000 align 2**2
15 ELF-x86-64: LOAD off 0x0000000000000000 vaddr 0x0000000000400000 paddr 0x0000000000400000 al…
17 ELF-x86-64: EH_FRAME off 0x00000000000000f4 vaddr 0x00000000004000f4 paddr 0x00000000004000f4 al…
19 ELF-x86-64: STACK off 0x0000000000000000 vaddr 0x0000000000000000 paddr 0x0000000000000000 al…
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dstore-clobbers-load.ll4 ; "load vaddr" depends on the store, so we should not mark vaddr as amdgpu.noclobber.
7 ; OPT: %vaddr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %input, i64 0, !amdgpu.unifor…
8 ; OPT-NEXT: %zero = load <4 x i32>, <4 x i32> addrspace(1)* %vaddr, align 16
13 %vaddr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %input, i64 0
14 %zero = load <4 x i32>, <4 x i32> addrspace(1)* %vaddr, align 16
H A Dverify-image-vaddr-align.mir3 # GFX90A-ERR: *** Bad machine code: Subtarget requires even aligned vector registers for vaddr oper…
5 # GFX90A-ERR: *** Bad machine code: Subtarget requires even aligned vector registers for vaddr oper…
7 # GFX90A-ERR: *** Bad machine code: Subtarget requires even aligned vector registers for vaddr oper…
9 # GFX90A-ERR: *** Bad machine code: Subtarget requires even aligned vector registers for vaddr oper…
11 # GFX90A-ERR: *** Bad machine code: Subtarget requires even aligned vector registers for vaddr oper…
/llvm-project-15.0.7/llvm/test/tools/llvm-objdump/
H A Dopenbsd-headers.test6 # CHECK: OPENBSD_RANDOMIZE off 0x0000000000000000 vaddr 0x0000000000000000 paddr 0x00000000…
8 # CHECK-NEXT: OPENBSD_WXNEEDED off 0x0000000000000000 vaddr 0x0000000000000000 paddr 0x000000000…
10 # CHECK-NEXT: OPENBSD_BOOTDATA off 0x0000000000000000 vaddr 0x0000000000000000 paddr 0x000000000…
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DFLATInstructions.td106 bits<8> vaddr;
165 (ins VReg_64:$vaddr)),
252 !if(EnableSaddr, (ins SReg_64:$saddr, VGPR_32:$vaddr), (ins VReg_64:$vaddr)),
480 " $vaddr, $vdata$offset$cpol">,
934 (inst $vaddr, $offset)
939 (inst $vaddr, $offset, 0, $in)
944 (inst $vaddr, $offset, 0, $in)
954 (inst $vaddr, $offset)
1062 (inst $vaddr, $offset)
1067 (inst $vaddr, $offset, 0, $in)
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-objdump/X86/
H A Dphdrs.test17 CHECK: RELRO off 0x0000000000001000 vaddr 0x0000000000201000 paddr 0x0000000000201000 align 2**0
31 NOTE: NOTE off 0x0000000000000200 vaddr 0x0000000000000200 paddr 0x0000000000000200 align 2**0

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