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/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dmma-acc-spill.ll23 ; CHECK-NEXT: .cfi_offset v30, -48
30 ; CHECK-NEXT: stxv v30, 128(r1) # 16-byte Folded Spill
33 ; CHECK-NEXT: vmr v30, v4
36 ; CHECK-NEXT: xxlor vs2, v30, v30
48 ; CHECK-NEXT: xvf16ger2pp acc0, v28, v30
50 ; CHECK-NEXT: lxv v30, 128(r1) # 16-byte Folded Reload
74 ; CHECK-BE-NEXT: .cfi_offset v30, -48
81 ; CHECK-BE-NEXT: stxv v30, 208(r1) # 16-byte Folded Spill
84 ; CHECK-BE-NEXT: vmr v30, v4
87 ; CHECK-BE-NEXT: xxlor vs2, v30, v30
[all …]
H A Dfp-strict-round.ll214 ; P8-NEXT: .cfi_offset v30, -32
228 ; P8-NEXT: xxlor v30, f1, f1
233 ; P8-NEXT: xxmrghd vs0, vs1, v30
239 ; P8-NEXT: xxlor v30, f1, f1
244 ; P8-NEXT: xxmrghd vs0, v30, vs1
266 ; P9-NEXT: .cfi_offset v30, -32
318 ; P8-NEXT: .cfi_offset v30, -32
328 ; P8-NEXT: xxlor v30, f1, f1
335 ; P8-NEXT: xxmrghd v2, v30, vs1
351 ; P9-NEXT: .cfi_offset v30, -32
[all …]
H A Df128-compare.ll522 ; CHECK-P8-NEXT: xxswapd v30, vs1
524 ; CHECK-P8-NEXT: vmr v3, v30
531 ; CHECK-P8-NEXT: vmr v31, v30
587 ; CHECK-P8-NEXT: vmr v3, v30
594 ; CHECK-P8-NEXT: vmr v31, v30
651 ; CHECK-P8-NEXT: vmr v3, v30
658 ; CHECK-P8-NEXT: vmr v31, v30
715 ; CHECK-P8-NEXT: vmr v3, v30
722 ; CHECK-P8-NEXT: vmr v31, v30
778 ; CHECK-P8-NEXT: vmr v3, v30
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dvec-cmpsel.ll11 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0
23 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0
34 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0
74 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0
85 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0
97 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0
109 ; CHECK-NEXT: vsel %v24, %v28, %v30, %v0
145 ; CHECK-NEXT: vceqh %v0, %v26, %v30
244 ; CHECK-NEXT: vceqf %v0, %v26, %v30
293 ; CHECK-NEXT: vceqg %v0, %v26, %v30
[all …]
H A Dvec-mul-02.ll11 ; CHECK: vmalb %v24, %v26, %v28, %v30
22 ; CHECK: vmalhw %v24, %v26, %v28, %v30
33 ; CHECK: vmalf %v24, %v26, %v28, %v30
44 ; CHECK: vfmadb %v24, %v26, %v28, %v30
56 ; CHECK: vfmsdb %v24, %v26, %v28, %v30
H A Dvec-cmp-cmp-logic-select.ll121 ; CHECK-NEXT: vceqb %v1, %v28, %v30
137 ; CHECK-NEXT: vceqb %v1, %v28, %v30
264 ; CHECK-NEXT: vceqg %v1, %v28, %v30
281 ; CHECK-NEXT: vceqg %v1, %v28, %v30
329 ; CHECK-NEXT: vceqh %v1, %v28, %v30
580 ; CHECK-DAG: vmrlf [[REG12:%v[0-9]+]], %v30, %v30
585 ; CHECK-DAG: vmrhf [[REG17:%v[0-9]+]], %v30, %v30
623 ; CHECK-NEXT: vmrlf %v1, %v30, %v30
628 ; CHECK-NEXT: vmrhf %v2, %v30, %v30
681 ; CHECK-NEXT: vmrlf %v17, %v30, %v30
[all …]
H A Dvec-cmp-01.ll115 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
127 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
139 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
151 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
163 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
175 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
187 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
199 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
211 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
223 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
H A Dvec-cmp-02.ll115 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
127 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
139 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
151 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
163 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
175 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
187 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
199 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
211 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
223 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
H A Dvec-cmp-03.ll115 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
127 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
139 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
151 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
163 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
175 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
187 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
199 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
211 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
223 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
H A Dvec-cmp-04.ll115 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
127 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
139 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
151 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
163 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
175 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
187 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
199 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
211 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
223 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
H A Dvec-mul-05.ll12 ; CHECK: vfnmadb %v24, %v26, %v28, %v30
25 ; CHECK: vfnmsdb %v24, %v26, %v28, %v30
39 ; CHECK: vfnmasb %v24, %v26, %v28, %v30
52 ; CHECK: vfnmssb %v24, %v26, %v28, %v30
H A Dvec-cmp-06.ll168 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
182 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
194 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
206 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
218 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
230 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
244 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
256 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
268 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
280 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
[all …]
H A Dvec-cmp-07.ll168 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
182 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
194 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
206 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
218 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
230 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
244 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
256 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
268 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
280 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
[all …]
H A Dvec-strict-mul-05.ll12 ; CHECK: vfnmadb %v24, %v26, %v28, %v30
28 ; CHECK: vfnmsdb %v24, %v26, %v28, %v30
45 ; CHECK: vfnmasb %v24, %v26, %v28, %v30
61 ; CHECK: vfnmssb %v24, %v26, %v28, %v30
H A Dvec-strict-cmp-03.ll210 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
227 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
242 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
257 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
272 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
287 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
304 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
319 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
334 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
349 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
[all …]
H A Dvec-strict-cmp-02.ll210 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
227 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
242 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
257 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
272 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
287 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
304 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
319 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
334 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
349 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
[all …]
H A Dvec-strict-cmps-01.ll210 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
227 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
242 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
257 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
272 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
287 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
304 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
319 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
334 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
349 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
[all …]
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Dnoneon-diagnostics.s5 fmla v1.2d, v30.2d, v20.2d
18 fmls v1.2d, v30.2d, v20.2d
33 fmls.2d v1, v30, v20
H A Darmv8.2a-crypto-apple.s8 rax1.2d v30, v29, v26
28 sm3partw1.4s v30, v29, v26
29 sm3partw2.4s v30, v29, v26
H A Darmv8.2a-crypto.s18 rax1 v30.2d, v29.2d, v26.2d
46 sm3partw1 v30.4s, v29.4s, v26.4s
47 sm3partw2 v30.4s, v29.4s, v26.4s
H A Darmv8.6a-simd-matmul.s18 usdot v3.2s, v15.8b, v30.8b
19 usdot v3.4s, v15.16b, v30.16b
H A Darmv8.6a-simd-matmul-error.s11 usdot v3.4s, v15.8b, v30.8b
13 usdot v3.2s, v15.16b, v30.16b
/llvm-project-15.0.7/llvm/test/MC/Hexagon/
H A Dv60-shift.s29 #CHECK: 1e02defb { v27.uh = vcl0(v30.uh) }
30 v27.uh=vcl0(v30.uh)
32 #CHECK: 1e03de90 { v16.w = vnormamt(v30.w) }
33 v16.w=vnormamt(v30.w)
H A Dv60-vmpy1.s8 #CHECK: 1936de0d { v13.w = vdmpy(v30.h,{{ *}}r22.uh):sat }
9 v13.w=vdmpy(v30.h,r22.uh):sat
71 #CHECK: 1946de76 { v23:22.uw = vmpy(v30.uh,{{ *}}r6.uh) }
72 v23:22.uw=vmpy(v30.uh,r6.uh)
125 #CHECK: 1fdeda10 { v16.w = vmpyie(v26.w{{ *}},{{ *}}v30.uh) }
126 v16.w=vmpyie(v26.w,v30.uh)
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-copy-tuple.ll19 …{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
22 …{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
36 …{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
39 …{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
53 …{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30}"()
90 …{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
93 …{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
109 …{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
112 …{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
122 ; CHECK: mov.16b v1, v30
[all …]

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