Searched refs:uabd (Results 1 – 21 of 21) sorted by relevance
12 uabd z31.b, p7/m, z31.b, z31.b label18 uabd z31.h, p7/m, z31.h, z31.h label24 uabd z31.s, p7/m, z31.s, z31.s label30 uabd z31.d, p7/m, z31.d, z31.d label46 uabd z4.d, p7/m, z4.d, z31.d label58 uabd z4.d, p7/m, z4.d, z31.d label
3 uabd z0.b, p8/m, z0.b, z0.b label
40 uabd v0.8b, v1.8b, v2.8b41 uabd v0.16b, v1.16b, v2.16b42 uabd v0.4h, v1.4h, v2.4h43 uabd v0.8h, v1.8h, v2.8h44 uabd v0.2s, v1.2s, v2.2s45 uabd v0.4s, v1.4s, v2.4s
357 uabd.8b v0, v0, v0428 ; CHECK: uabd.8b v0, v0, v0 ; encoding: [0x00,0x74,0x20,0x2e]
323 uabd v0.4s, v1.2s, v2.2s
4 declare <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8>, <8 x i8>)10 ; CHECK-NEXT: uabd v0.8b, v0.8b, v1.8b45 declare <16 x i8> @llvm.aarch64.neon.uabd.v16i8(<16 x i8>, <16 x i8>)51 ; CHECK-NEXT: uabd v0.16b, v0.16b, v1.16b86 declare <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16>, <4 x i16>)92 ; CHECK-NEXT: uabd v0.4h, v0.4h, v1.4h127 declare <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16>, <8 x i16>)133 ; CHECK-NEXT: uabd v0.8h, v0.8h, v1.8h168 declare <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32>, <2 x i32>)174 ; CHECK-NEXT: uabd v0.2s, v0.2s, v1.2s[all …]
108 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)155 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)200 ; CHECK-NEXT: uabd.16b v0, v0, v1261 ; CHECK-NEXT: uabd.8h v0, v0, v1334 ; CHECK-NEXT: uabd.4s v0, v0, v1578 ; CHECK-NEXT: uabd.8b v0, v0, v1591 ; CHECK-NEXT: uabd.16b v0, v0, v1604 ; CHECK-NEXT: uabd.4h v0, v0, v1617 ; CHECK-NEXT: uabd.8h v0, v0, v1630 ; CHECK-NEXT: uabd.2s v0, v0, v1[all …]
325 ; CHECK: uabd z0.b, p0/m, z0.b, z1.b327 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uabd.nxv16i8(<vscale x 16 x i1> %pg,335 ; CHECK: uabd z0.h, p0/m, z0.h, z1.h337 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uabd.nxv8i16(<vscale x 8 x i1> %pg,345 ; CHECK: uabd z0.s, p0/m, z0.s, z1.s347 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uabd.nxv4i32(<vscale x 4 x i1> %pg,355 ; CHECK: uabd z0.d, p0/m, z0.d, z1.d357 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uabd.nxv2i64(<vscale x 2 x i1> %pg,403 declare <vscale x 16 x i8> @llvm.aarch64.sve.uabd.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>,…404 declare <vscale x 8 x i16> @llvm.aarch64.sve.uabd.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>,…[all …]
134 ; CHECK-NEXT: uabd z0.b, p0/m, z0.b, z1.b150 ; CHECK-NEXT: uabd z0.b, p2/m, z0.b, z1.b163 ; CHECK-NEXT: uabd z0.h, p0/m, z0.h, z1.h179 ; CHECK-NEXT: uabd z0.h, p0/m, z0.h, z1.h192 ; CHECK-NEXT: uabd z0.s, p0/m, z0.s, z1.s208 ; CHECK-NEXT: uabd z0.s, p0/m, z0.s, z1.s221 ; CHECK-NEXT: uabd z0.d, p0/m, z0.d, z1.d237 ; CHECK-NEXT: uabd z0.d, p0/m, z0.d, z1.d279 ; CHECK-NEXT: uabd z0.s, p0/m, z0.s, z1.s
196 ; CHECK-NEXT: uabd v0.8b, v0.8b, v1.8b209 ; CHECK-NEXT: uabd v0.16b, v0.16b, v1.16b222 ; CHECK-NEXT: uabd v0.4h, v0.4h, v1.4h237 ; CHECK-NEXT: uabd v0.4h, v0.4h, v1.4h249 ; CHECK-NEXT: uabd v0.8h, v0.8h, v1.8h274 ; CHECK-NEXT: uabd v0.2s, v0.2s, v1.2s290 ; CHECK-NEXT: uabd v0.2s, v0.2s, v1.2s302 ; CHECK-NEXT: uabd v0.4s, v0.4s, v1.4s
212 …%2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uabd.nxv16i8(<vscale x 16 x i1> %1, <vscale x 16 x …252 …%2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uabd.nxv8i16(<vscale x 8 x i1> %1, <vscale x 8 x i1…292 …%2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uabd.nxv4i32(<vscale x 4 x i1> %1, <vscale x 4 x i3…332 …%2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uabd.nxv2i64(<vscale x 2 x i1> %1, <vscale x 2 x i6…371 declare <vscale x 16 x i8> @llvm.aarch64.sve.uabd.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <…372 declare <vscale x 8 x i16> @llvm.aarch64.sve.uabd.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <v…373 declare <vscale x 4 x i32> @llvm.aarch64.sve.uabd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <v…374 declare <vscale x 2 x i64> @llvm.aarch64.sve.uabd.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <v…
18 declare <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32>, <2 x i32>)19 declare <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16>, <4 x i16>)20 declare <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8>, <8 x i8>)1664 %vabd.i.i = tail call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %a, <8 x i8> %b)1675 %vabd2.i.i = tail call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %a, <4 x i16> %b)1686 %vabd2.i.i = tail call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %a, <2 x i32> %b)1733 %vabd.i.i.i = tail call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %b, <8 x i8> %c)1745 %vabd2.i.i.i = tail call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %b, <4 x i16> %c)1757 %vabd2.i.i.i = tail call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %b, <2 x i32> %c)1810 …%vabd.i.i.i = tail call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %shuffle.i.i, <8 x i8> %shu…[all …]
8 declare <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8>, <8 x i8>)408 …%vabd.i.i.i = tail call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %shuffle.i.i, <8 x i8> %shu…
826 uabd v0.4h, v0.4h, v0.4h label1895 # CHECK-NEXT: 1 3 0.50 uabd v0.4h, v0.4h, v0.4h2975 … - - 0.50 0.50 - - - - - - uabd v0.4h, v0.4h, v0.4h
826 uabd v0.4h, v0.4h, v0.4h label1895 # CHECK-NEXT: 1 2 0.50 uabd v0.4h, v0.4h, v0.4h2976 … - - - - - - - - 0.50 0.50 uabd v0.4h, v0.4h, v0.4h
3423 uabd z31.b, p7/m, z31.b, z31.b label3424 uabd z31.d, p7/m, z31.d, z31.d label3425 uabd z31.h, p7/m, z31.h, z31.h label3426 uabd z31.s, p7/m, z31.s, z31.s label7350 # CHECK-NEXT: 1 2 0.50 uabd z31.b, p7/m, z31.b, z31.b7351 # CHECK-NEXT: 1 2 0.50 uabd z31.d, p7/m, z31.d, z31.d7352 # CHECK-NEXT: 1 2 0.50 uabd z31.h, p7/m, z31.h, z31.h7353 # CHECK-NEXT: 1 2 0.50 uabd z31.s, p7/m, z31.s, z31.s11289 … - - - - - - - - 0.50 0.50 uabd z31.b, p7/m, z31.b,…11290 … - - - - - - - - 0.50 0.50 uabd z31.d, p7/m, z31.d,…[all …]
149 # CHECK: uabd v15.4h, v16.4h, v17.4h
340 # CHECK: uabd.8b v0, v0, v0
3744 // [486] "uabd $Zdn, $Pg/m, $_Zdn, $Zm";
491 …defm UABD_ZPmZ : sve_int_bin_pred_arit_1<0b101, "uabd", "UABD_ZPZZ", int_aarch64_sve_uabd, Destruc…
4630 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", AArch64uabd>;