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/llvm-project-15.0.7/polly/test/CodeGen/
H A Dpartial_write_impossible_restriction___%for.body344---%if.then.i.i1141.loopexit.jscop.transformed14 "context" : "[tmp5] -> { : -2147483648 <= tmp5 <= 2147483647 }",
21 "relation" : "[tmp5] -> { Stmt_for_body344[-1 + tmp5] -> MemRef__pn[-1 + tmp5] }"
24 … "domain" : "[tmp5] -> { Stmt_for_body344[i0] : 0 <= i0 < tmp5; Stmt_for_body344[0] : tmp5 <= 0 }",
26 …"schedule" : "[tmp5] -> { Stmt_for_body344[i0] -> [i0, 0] : i0 < tmp5; Stmt_for_body344[0] -> [0, …
36 …"relation" : "[tmp5] -> { Stmt_cond_false[i0] -> MemRef__pn[i0] : i0 <= -2 + tmp5; Stmt_cond_false…
39 …"domain" : "[tmp5] -> { Stmt_cond_false[i0] : 0 <= i0 <= -2 + tmp5; Stmt_cond_false[0] : tmp5 <= 0…
41 …"schedule" : "[tmp5] -> { Stmt_cond_false[i0] -> [i0, 1] : i0 <= -2 + tmp5; Stmt_cond_false[0] -> …
47 "relation" : "[tmp5] -> { Stmt_cond_end[i0] -> MemRef__pn[i0] }"
51 "relation" : "[tmp5] -> { Stmt_cond_end[i0] -> MemRef__pn[i0] }"
54 … "domain" : "[tmp5] -> { Stmt_cond_end[i0] : 0 <= i0 < tmp5; Stmt_cond_end[0] : tmp5 <= 0 }",
[all …]
H A Dpartial_write_impossible_restriction___%for.body344---%if.then.i.i1141.loopexit.jscop14 "context" : "[tmp5] -> { : -2147483648 <= tmp5 <= 2147483647 }",
21 … "relation" : "[tmp5] -> { Stmt_for_body344[i0] -> MemRef_cond_in_sroa_speculated__phi[] }"
24 … "domain" : "[tmp5] -> { Stmt_for_body344[i0] : 0 <= i0 < tmp5; Stmt_for_body344[0] : tmp5 <= 0 }",
26 …"schedule" : "[tmp5] -> { Stmt_for_body344[i0] -> [i0, 0] : i0 < tmp5; Stmt_for_body344[0] -> [0, …
32 "relation" : "[tmp5] -> { Stmt_cond_false[i0] -> MemRef_tmp4[1 + i0] }"
39 …"domain" : "[tmp5] -> { Stmt_cond_false[i0] : 0 <= i0 <= -2 + tmp5; Stmt_cond_false[0] : tmp5 <= 0…
41 …"schedule" : "[tmp5] -> { Stmt_cond_false[i0] -> [i0, 1] : i0 <= -2 + tmp5; Stmt_cond_false[0] -> …
47 … "relation" : "[tmp5] -> { Stmt_cond_end[i0] -> MemRef_cond_in_sroa_speculated__phi[] }"
51 "relation" : "[tmp5] -> { Stmt_cond_end[i0] -> MemRef__pn[i0] }"
54 … "domain" : "[tmp5] -> { Stmt_cond_end[i0] : 0 <= i0 < tmp5; Stmt_cond_end[0] : tmp5 <= 0 }",
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dvaba.ll11 ret <8 x i8> %tmp5
22 ret <4 x i16> %tmp5
33 ret <2 x i32> %tmp5
44 ret <8 x i8> %tmp5
55 ret <4 x i16> %tmp5
66 ret <2 x i32> %tmp5
77 ret <16 x i8> %tmp5
88 ret <8 x i16> %tmp5
99 ret <4 x i32> %tmp5
110 ret <16 x i8> %tmp5
[all …]
H A Dvmls.ll10 %tmp5 = sub <8 x i8> %A, %tmp4
11 ret <8 x i8> %tmp5
20 %tmp5 = sub <4 x i16> %A, %tmp4
21 ret <4 x i16> %tmp5
30 %tmp5 = sub <2 x i32> %A, %tmp4
31 ret <2 x i32> %tmp5
41 ret <2 x float> %tmp5
51 ret <16 x i8> %tmp5
61 ret <8 x i16> %tmp5
71 ret <4 x i32> %tmp5
[all …]
H A Dvmla.ll10 %tmp5 = add <8 x i8> %A, %tmp4
11 ret <8 x i8> %tmp5
20 %tmp5 = add <4 x i16> %A, %tmp4
21 ret <4 x i16> %tmp5
30 %tmp5 = add <2 x i32> %A, %tmp4
31 ret <2 x i32> %tmp5
41 ret <2 x float> %tmp5
51 ret <16 x i8> %tmp5
61 ret <8 x i16> %tmp5
71 ret <4 x i32> %tmp5
[all …]
H A Duxtb.ll61 %tmp5 = and i32 %tmp4, 16711680
62 %tmp6 = or i32 %tmp2, %tmp5
74 %tmp5 = and i32 %tmp4, 16711680
75 %tmp6 = or i32 %tmp2, %tmp5
86 %tmp5 = lshr i32 %x, 24
87 %tmp6 = or i32 %tmp2, %tmp5
98 %tmp5 = and i32 %tmp4, 16711680
99 %tmp6 = or i32 %tmp5, %tmp1
118 %tmp5 = and i32 %tmp4, 458759
119 %tmp7 = or i32 %tmp5, %tmp2
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A D2007-03-15-GEP-Idx-Sink.ll15 %tmp5.sum72 = add i32 %col, 7 ; <i32> [#uses=1]
16 %tmp5.sum71 = add i32 %col, 5 ; <i32> [#uses=1]
17 %tmp5.sum70 = add i32 %col, 3 ; <i32> [#uses=1]
18 %tmp5.sum69 = add i32 %col, 2 ; <i32> [#uses=1]
19 %tmp5.sum68 = add i32 %col, 1 ; <i32> [#uses=1]
20 %tmp5.sum66 = add i32 %col, 4 ; <i32> [#uses=1]
21 %tmp5.sum = add i32 %col, 6 ; <i32> [#uses=1]
30 %tmp5 = getelementptr i8, ptr %tmp3, i32 %col ; <ptr> [#uses=1]
32 store i8 %tmp7, ptr %tmp5
36 %tmp15 = getelementptr i8, ptr %tmp3, i32 %tmp5.sum72 ; <ptr> [#uses=1]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dneon-addlv.ll31 %tmp5 = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %tmp3)
32 ret i16 %tmp5
45 ret i16 %tmp5
58 ret i32 %tmp5
71 ret i64 %tmp5
84 ret i32 %tmp5
99 ret i16 %tmp5
112 ret i16 %tmp5
125 ret i32 %tmp5
138 ret i64 %tmp5
[all …]
H A Darm64-zip.ll12 %tmp5 = add <8 x i8> %tmp3, %tmp4
13 ret <8 x i8> %tmp5
25 %tmp5 = add <4 x i16> %tmp3, %tmp4
26 ret <4 x i16> %tmp5
38 %tmp5 = add <16 x i8> %tmp3, %tmp4
39 ret <16 x i8> %tmp5
52 ret <8 x i16> %tmp5
65 ret <4 x i32> %tmp5
78 ret <4 x float> %tmp5
93 ret <8 x i8> %tmp5
[all …]
H A Darm64-uzp.ll12 %tmp5 = add <8 x i8> %tmp3, %tmp4
13 ret <8 x i8> %tmp5
25 %tmp5 = add <4 x i16> %tmp3, %tmp4
26 ret <4 x i16> %tmp5
38 %tmp5 = add <16 x i8> %tmp3, %tmp4
39 ret <16 x i8> %tmp5
52 ret <8 x i16> %tmp5
65 ret <4 x i32> %tmp5
78 ret <4 x float> %tmp5
93 ret <8 x i8> %tmp5
[all …]
H A Dload-combine.ll17 %tmp6 = zext i8 %tmp5 to i32
46 %tmp6 = zext i8 %tmp5 to i32
76 %tmp6 = zext i8 %tmp5 to i32
103 %tmp5 = zext i8 %tmp4 to i64
153 %tmp6 = zext i8 %tmp5 to i64
202 %tmp6 = zext i8 %tmp5 to i32
232 %tmp6 = zext i8 %tmp5 to i32
263 %tmp6 = zext i8 %tmp5 to i32
294 %tmp6 = zext i8 %tmp5 to i32
330 %tmp7 = or i32 %tmp6, %tmp5
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/
H A Dno-return-blocks.ll3 ; CHECK: DIVERGENT: %tmp5 = getelementptr inbounds float, float addrspace(1)* %arg, i64 %tmp2
4 ; CHECK: DIVERGENT: %tmp10 = load volatile float, float addrspace(1)* %tmp5, align 4
5 ; CHECK: DIVERGENT: %tmp11 = load volatile float, float addrspace(1)* %tmp5, align 4
12 %tmp5 = getelementptr inbounds float, float addrspace(1)* %arg, i64 %tmp2
13 %tmp6 = load volatile float, float addrspace(1)* %tmp5, align 4
18 %tmp10 = load volatile float, float addrspace(1)* %tmp5, align 4
22 %tmp11 = load volatile float, float addrspace(1)* %tmp5, align 4
/llvm-project-15.0.7/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/
H A Dno-return-blocks.ll3 ; CHECK: DIVERGENT: %tmp5 = getelementptr inbounds float, float addrspace(1)* %arg, i64 %tmp2
4 ; CHECK: DIVERGENT: %tmp10 = load volatile float, float addrspace(1)* %tmp5, align 4
5 ; CHECK: DIVERGENT: %tmp11 = load volatile float, float addrspace(1)* %tmp5, align 4
12 %tmp5 = getelementptr inbounds float, float addrspace(1)* %arg, i64 %tmp2
13 %tmp6 = load volatile float, float addrspace(1)* %tmp5, align 4
18 %tmp10 = load volatile float, float addrspace(1)* %tmp5, align 4
22 %tmp11 = load volatile float, float addrspace(1)* %tmp5, align 4
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dint-cmp-56.ll19 %tmp5 = icmp eq i32 %tmp4, 0
20 br i1 %tmp5, label %bb4, label %bb2
46 %tmp5 = icmp eq i32 %tmp4, 0
47 br i1 %tmp5, label %bb4, label %bb2
73 %tmp5 = icmp eq i32 %tmp4, 0
74 br i1 %tmp5, label %bb4, label %bb2
100 %tmp5 = icmp eq i32 %tmp4, 0
101 br i1 %tmp5, label %bb4, label %bb2
126 %tmp5 = icmp eq i32 %tmp4, 0
127 br i1 %tmp5, label %bb4, label %bb2
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dalignbit-pat.ll13 %tmp5 = lshr i64 %tmp, %tmp4
14 %tmp6 = trunc i64 %tmp5 to i32
33 %tmp5 = lshr i64 %tmp, %tmp4
34 %tmp6 = trunc i64 %tmp5 to i32
49 %tmp5 = lshr i64 %tmp, %tmp4
50 %tmp6 = trunc i64 %tmp5 to i32
65 %tmp5 = lshr i64 %tmp, %tmp4
66 %tmp6 = trunc i64 %tmp5 to i32
78 %tmp5 = lshr i64 %tmp, 30
79 %tmp6 = trunc i64 %tmp5 to i32
[all …]
H A Dwaitcnt-vscnt.ll21 %tmp5 = add nuw nsw i64 %tmp2, 4294967296
22 %tmp6 = lshr exact i64 %tmp5, 32
96 %tmp5 = add nuw nsw i64 %tmp2, 4294967296
97 %tmp6 = lshr exact i64 %tmp5, 32
117 store i32 0, i32* %tmp5, align 4
141 store i32 0, i32* %tmp5, align 4
169 store i32 0, i32* %tmp5, align 4
195 %tmp5 = add nuw nsw i64 %tmp2, 4294967296
196 %tmp6 = lshr exact i64 %tmp5, 32
214 %tmp5 = add nuw nsw i64 %tmp2, 4294967296
[all …]
H A Dload-select-ptr.ll24 %tmp5 = select i1 %tmp2, i64 %tmp3, i64 %tmp4
25 store i64 %tmp5, i64 addrspace(1)* %ptr2, align 8
45 %tmp5 = select i1 %tmp2, i64 %tmp3, i64 %tmp4
46 store i64 %tmp5, i64 addrspace(1)* %ptr2, align 8
60 %tmp5 = select i1 %tmp2, i64 %tmp3, i64 %tmp4
61 store i64 %tmp5, i64 addrspace(1)* %ptr2, align 8
79 %tmp5 = select i1 %tmp2, i64 %tmp3, i64 %tmp4
80 store i64 %tmp5, i64 addrspace(1)* %ptr2, align 8
/llvm-project-15.0.7/llvm/test/Transforms/Reassociate/
H A Drepeats.ll71 %tmp5 = mul i3 %tmp4, %x
72 ret i3 %tmp5
85 %tmp5 = mul i3 %tmp4, %x
86 %tmp6 = mul i3 %tmp5, %x
100 %tmp5 = mul i4 %tmp4, %x
101 %tmp6 = mul i4 %tmp5, %x
117 %tmp5 = mul i4 %tmp4, %x
118 %tmp6 = mul i4 %tmp5, %x
135 %tmp5 = mul i4 %tmp4, %x
136 %tmp6 = mul i4 %tmp5, %x
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/BasicAA/
H A Dfull-store-partial-alias.ll6 ; so the %tmp5 load is PartialAlias with the store and suppress TBAA.
7 ; Without BasicAA, TBAA should say that %tmp5 is NoAlias with the store.
17 ; BASICAA: ret i32 %tmp5.lobit
27 %tmp5 = load i32, i32* %arrayidx, align 4, !tbaa !3
28 %tmp5.lobit = lshr i32 %tmp5, 31
29 ret i32 %tmp5.lobit
/llvm-project-15.0.7/polly/test/ScopDetect/
H A Dcollective_invariant_loads.ll8 ;CHECK-NEXT: [tmp5] -> { Stmt_bb2[i0, i1] -> MemRef_arg[1] };
9 ;CHECK-NEXT: Execution Context: [tmp5] -> { : }
11 ;CHECK-NEXT: [tmp5] -> { Stmt_bb2[i0, i1] -> MemRef_tmp3[9] };
12 ;CHECK-NEXT: Execution Context: [tmp5] -> { : }
14 ;CHECK-NEXT: [tmp5] -> { Stmt_bb2[i0, i1] -> MemRef_tmp3[2] };
15 ;CHECK-NEXT: Execution Context: [tmp5] -> { : }
38 %tmp5 = load i64, i64* %tmp4, align 8
39 %tmp6 = mul nsw i64 %tmp5, %.0
/llvm-project-15.0.7/llvm/test/Analysis/CFLAliasAnalysis/Steensgaard/
H A Dfull-store-partial-alias.ll6 ; so the %tmp5 load is PartialAlias with the store and suppress TBAA.
8 ; Without CFL AA, TBAA should say that %tmp5 is NoAlias with the store.
18 ; FIXME: This would be ret i32 %tmp5.lobit if CFLSteensAA could prove PartialAlias
29 %tmp5 = load i32, i32* %arrayidx, align 4, !tbaa !3
30 %tmp5.lobit = lshr i32 %tmp5, 31
31 ret i32 %tmp5.lobit
/llvm-project-15.0.7/llvm/test/SafepointIRVerifier/
H A Dhidden-constant-base.ll10 %tmp = phi i8 addrspace(1)* [ %tmp5.relocated, %bb8 ], [ null, %bb ]
15 %tmp5 = phi i8 addrspace(1)* [ %tmp5.relocated, %bb8 ], [ %tmp, %bb2 ]
16 … i32 0, i32 0, i32 0, i32 0) [ "deopt"(i8 addrspace(1)* %tmp5), "gc-live"(i8 addrspace(1)* %tmp5) ]
18 …%tmp5.relocated = call coldcc i8 addrspace(1)* @llvm.experimental.gc.relocate.p1i8(token %statepoi…
/llvm-project-15.0.7/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/
H A Dmultiple_tails.ll19 %tmp5 = getelementptr [16384 x i32], [16384 x i32] addrspace(3)* @0, i32 0, i32 %tmp4
22 store i32 0, i32 addrspace(3)* %tmp5, align 4
23 store i32 0, i32 addrspace(3)* %tmp5, align 4
24 store i32 0, i32 addrspace(3)* %tmp5, align 4
58 %tmp5 = getelementptr [16384 x i32], [16384 x i32] addrspace(3)* @0, i32 0, i32 %a4
67 %l6 = load i32, i32 addrspace(3)* %tmp5, align 4
68 %l7 = load i32, i32 addrspace(3)* %tmp5, align 4
69 %l8 = load i32, i32 addrspace(3)* %tmp5, align 4
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/
H A Dspeculate-with-offset.ll20 %tmp5 = load i64*, i64** %__a.addr, align 8
24 %storemerge = phi i64* [ undef, %if.then ], [ %tmp5, %if.end ]
42 %tmp5 = load i64*, i64** %__a.addr, align 8
46 %storemerge = phi i64* [ undef, %if.then ], [ %tmp5, %if.end ]
64 %tmp5 = load i64*, i64** %__a.addr, align 8
68 %storemerge = phi i64* [ undef, %if.then ], [ %tmp5, %if.end ]
86 %tmp5 = load i64*, i64** %__a.addr, align 8
90 %storemerge = phi i64* [ undef, %if.then ], [ %tmp5, %if.end ]
/llvm-project-15.0.7/llvm/test/Transforms/LowerExpectIntrinsic/
H A Dphi_tern.ll10 %tmp5 = icmp sgt i32 %arg, %arg1
11 br i1 %tmp5, label %bb9, label %bb7
12 ; CHECK: br i1 %tmp5{{.*}}!prof [[WEIGHT:![0-9]+]]
28 %tmp5 = icmp sgt i32 %arg, %arg1
29 br i1 %tmp5, label %bb6, label %bb7
30 ; CHECK: br i1 %tmp5{{.*}}!prof [[WEIGHT:![0-9]+]]

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