| /llvm-project-15.0.7/clang/test/CodeGenCUDA/ |
| H A D | texture.cu | 21 struct __attribute__((device_builtin_texture_type)) texture : public textureReference { struct
32 texture<float, 2, ElementType> tex;
33 texture<float, 2, NormalizedFloat> norm;
39 __attribute__((device)) v4f tex2d_ld(texture<float, 2, ElementType>, float, float) asm("llvm.nvvm.t…
40 __attribute__((device)) v4f tex2d_ld(texture<float, 2, NormalizedFloat>, int, int) asm("llvm.nvvm.t…
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| /llvm-project-15.0.7/clang/test/SemaCUDA/ |
| H A D | const-var.cu | 68 struct __attribute__((device_builtin_texture_type)) texture : public textureReference { struct
84 texture<float, 2, ElementType> tex;
98 __device__ static texture<float, 2, ElementType> *const p6;
109 __device__ texture<float, 2, ElementType> *const B::p6 = &tex;
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| H A D | constexpr-var.cu | 69 struct __attribute__((device_builtin_texture_type)) texture : public textureReference { struct
85 texture<float, 2, ElementType> tex;
102 __device__ static constexpr texture<float, 2, ElementType> *const p6 = &tex;
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| H A D | device-use-host-var.cu | 255 struct __attribute__((device_builtin_texture_type)) texture { struct
256 static texture<int> ref; argument
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| /llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/ |
| H A D | annotations.ll | 6 @texture = internal addrspace(1) global i64 0, align 8
7 ; CHECK: .global .texref texture
53 !9 = !{i64 addrspace(1)* @texture, !"texture", i32 1}
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| H A D | texsurf-queries.ll | 104 !1 = !{i64 addrspace(1)* @tex0, !"texture", i32 1}
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| H A D | tex-read-cuda.ll | 75 !3 = !{i64 addrspace(1)* @tex0, !"texture", i32 1}
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| /llvm-project-15.0.7/clang/test/Headers/Inputs/include/ |
| H A D | cuda.h | 142 struct __attribute__((device_builtin_texture_type)) texture enum
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| /llvm-project-15.0.7/clang/lib/Headers/ |
| H A D | __clang_cuda_texture_intrinsics.h | 696 texture<__DataT, __TexT, cudaReadModeNormalizedFloat> __handle,
709 texture<__DataT, __TexT, cudaReadModeElementType> __handle,
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPU.td | 44 "Support 128-bit texture resources"
765 // Sparse texture support requires that all result registers are zeroed when
772 "Enable zeroing of result registers for sparse texture fetches"
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| /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/ |
| H A D | cluster_stores.ll | 289 ; Cluster loads from the same texture with different coordinates
408 ; Cluster loads from the same texture and sampler with different coordinates
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| /llvm-project-15.0.7/llvm/docs/ |
| H A D | AMDGPUModifierSyntax.rst | 455 Specifies texture resource size. The default size is 256 bits.
462 r128 Specifies 128 bits texture resource size.
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| /llvm-project-15.0.7/llvm/include/llvm/IR/ |
| H A D | IntrinsicsAMDGPU.td | 537 // Represent texture/image types / dimensionality.
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| H A D | IntrinsicsNVVM.td | 1566 // For getting the handle from a texture or surface variable
3287 "llvm.nvvm.istypep.texture">,
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| /llvm-project-15.0.7/clang/include/clang/Basic/ |
| H A D | AttrDocs.td | 5926 template when declaring the texture reference. A texture reference variable
5928 into an internal texture object, which is established through texture bind and
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| H A D | DiagnosticSemaKinds.td | 8573 "illegal device builtin %select{surface|texture}0 reference "
8582 "illegal device builtin %select{surface|texture}0 reference "
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| /llvm-project-15.0.7/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXIntrinsics.td | 2223 // non-coherent texture cache, and therefore the values read must be read-only
2681 // NOTE: For Fermi support, any new texture/surface/sampler intrinsics must be
|