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/llvm-project-15.0.7/llvm/test/CodeGen/AVR/
H A Djmp-long.ll14 tail call addrspace(0) void asm sideeffect "nop", ""()
15 tail call addrspace(0) void asm sideeffect "nop", ""()
16 tail call addrspace(0) void asm sideeffect "nop", ""()
17 tail call addrspace(0) void asm sideeffect "nop", ""()
18 tail call addrspace(0) void asm sideeffect "nop", ""()
19 tail call addrspace(0) void asm sideeffect "nop", ""()
20 tail call addrspace(0) void asm sideeffect "nop", ""()
21 tail call addrspace(0) void asm sideeffect "nop", ""()
22 tail call addrspace(0) void asm sideeffect "nop", ""()
23 tail call addrspace(0) void asm sideeffect "nop", ""()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dloop-prefetch.ll27 tail call void @llvm.amdgcn.s.sleep(i32 0)
52 tail call void @llvm.amdgcn.s.sleep(i32 0)
53 tail call void @llvm.amdgcn.s.sleep(i32 0)
54 tail call void @llvm.amdgcn.s.sleep(i32 0)
55 tail call void @llvm.amdgcn.s.sleep(i32 0)
56 tail call void @llvm.amdgcn.s.sleep(i32 0)
57 tail call void @llvm.amdgcn.s.sleep(i32 0)
58 tail call void @llvm.amdgcn.s.sleep(i32 0)
59 tail call void @llvm.amdgcn.s.sleep(i32 0)
60 tail call void @llvm.amdgcn.s.sleep(i32 0)
[all …]
H A Dbranch-relax-spill.ll790 tail call void asm sideeffect "; reg use $0", "{s0}"(i32 %sgpr0) #0
791 tail call void asm sideeffect "; reg use $0", "{s1}"(i32 %sgpr1) #0
792 tail call void asm sideeffect "; reg use $0", "{s2}"(i32 %sgpr2) #0
793 tail call void asm sideeffect "; reg use $0", "{s3}"(i32 %sgpr3) #0
794 tail call void asm sideeffect "; reg use $0", "{s4}"(i32 %sgpr4) #0
795 tail call void asm sideeffect "; reg use $0", "{s5}"(i32 %sgpr5) #0
796 tail call void asm sideeffect "; reg use $0", "{s6}"(i32 %sgpr6) #0
797 tail call void asm sideeffect "; reg use $0", "{s7}"(i32 %sgpr7) #0
798 tail call void asm sideeffect "; reg use $0", "{s8}"(i32 %sgpr8) #0
799 tail call void asm sideeffect "; reg use $0", "{s9}"(i32 %sgpr9) #0
[all …]
H A Dpropagate-attributes-clone.ll15 ; OPT-EXT: tail call void @foo4()
16 ; OPT-EXT: tail call void @foo3()
114 tail call void @foo4()
115 tail call void @foo3()
116 tail call void @foo2()
117 tail call void @foo2()
118 tail call void @foo1()
119 tail call void @0()
125 tail call void @foo1()
131 tail call void @foo2()
[all …]
/llvm-project-15.0.7/llvm/test/Bitcode/
H A Dupgrade-arc-runtime-calls.ll15 %v0 = tail call i8* @objc_autorelease(i8* %a) #0
16 tail call void @objc_autoreleasePoolPop(i8* %a) #0
17 %v1 = tail call i8* @objc_autoreleasePoolPush() #0
19 tail call void @objc_copyWeak(i8** %b, i8** %c) #0
20 tail call void @objc_destroyWeak(i8** %b) #0
22 %v4 = tail call i8* @objc_loadWeak(i8** %b) #0
25 tail call void @objc_release(i8* %a) #0
26 %v6 = tail call i8* @objc_retain(i8* %a) #0
33 tail call void (...) @clang.arc.use(i8* %a) #0
39 %v17 = tail call i32 @objc_sync.enter(i8* %a) #0
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/BDCE/
H A Dbasic.ll10 %call = tail call signext i32 @foo(i32 signext 5) #0
13 %call1 = tail call signext i32 @foo(i32 signext 3) #0
16 %call4 = tail call signext i32 @foo(i32 signext 2) #0
34 ; CHECK: tail call signext i32 @foo(i32 signext 2)
35 ; CHECK: tail call signext i32 @foo(i32 signext 1)
36 ; CHECK: tail call signext i32 @foo(i32 signext 0)
37 ; CHECK: tail call signext i32 @foo(i32 signext 4)
80 ; CHECK: tail call signext i32 @goo(i32 signext 5)
83 ; CHECK: tail call signext i32 @goo(i32 signext 1)
84 ; CHECK: tail call signext i32 @goo(i32 signext 0)
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopUnroll/
H A Dignore-annotation-intrinsic-cost.ll27 %annot.0 = tail call i32 @llvm.annotation.i32(i32 %i.01, i8* null, i8* null, i32 0)
28 %annot.1 = tail call i32 @llvm.annotation.i32(i32 %i.01, i8* null, i8* null, i32 0)
29 %annot.2 = tail call i32 @llvm.annotation.i32(i32 %i.01, i8* null, i8* null, i32 0)
30 %annot.3 = tail call i32 @llvm.annotation.i32(i32 %i.01, i8* null, i8* null, i32 0)
31 %annot.4 = tail call i32 @llvm.annotation.i32(i32 %i.01, i8* null, i8* null, i32 0)
32 %annot.5 = tail call i32 @llvm.annotation.i32(i32 %i.01, i8* null, i8* null, i32 0)
33 %annot.6 = tail call i32 @llvm.annotation.i32(i32 %i.01, i8* null, i8* null, i32 0)
34 %annot.7 = tail call i32 @llvm.annotation.i32(i32 %i.01, i8* null, i8* null, i32 0)
35 %annot.8 = tail call i32 @llvm.annotation.i32(i32 %i.01, i8* null, i8* null, i32 0)
36 %annot.9 = tail call i32 @llvm.annotation.i32(i32 %i.01, i8* null, i8* null, i32 0)
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/Attributor/
H A Dheap_to_stack_gpu.ll46 tail call void @free(i8* %p2)
64 tail call void @free(i8* %1)
79 tail call void @free(i8* %1)
94 tail call void @free(i8* %1)
115 tail call void @free(i8* %1)
138 tail call void @free(i8* %1)
151 tail call void @free(i8* %1)
166 tail call void @free(i8* %1)
226 tail call void @free(i8* %2)
257 tail call void @free(i8* %2)
[all …]
H A Dheap_to_stack.ll100 ;tail call void @free(i8* %m)
111 tail call void @free(i8* %p2)
129 tail call void @free(i8* %1)
144 tail call void @free(i8* %1)
164 tail call void @free(i8* %1)
184 tail call void @free(i8* %1)
206 tail call void @free(i8* %1)
219 tail call void @free(i8* %1)
242 tail call void @free(i8* %1)
263 tail call void @free(i8* %1)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Generic/
H A DPBQP.ll5 %call = tail call i32 (...) @baz()
6 %call1 = tail call i32 (...) @baz()
7 %call2 = tail call i32 (...) @baz()
8 %call3 = tail call i32 (...) @baz()
9 %call4 = tail call i32 (...) @baz()
10 %call5 = tail call i32 (...) @baz()
11 %call6 = tail call i32 (...) @baz()
12 %call7 = tail call i32 (...) @baz()
13 %call8 = tail call i32 (...) @baz()
14 %call9 = tail call i32 (...) @baz()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dcbz-implicit-it-range.ll14 tail call void asm sideeffect "movseq r0, #0\0A", ""()
15 tail call void asm sideeffect "movseq r0, #0\0A", ""()
16 tail call void asm sideeffect "movseq r0, #0\0A", ""()
17 tail call void asm sideeffect "movseq r0, #0\0A", ""()
18 tail call void asm sideeffect "movseq r0, #0\0A", ""()
19 tail call void asm sideeffect "movseq r0, #0\0A", ""()
20 tail call void asm sideeffect "movseq r0, #0\0A", ""()
21 tail call void asm sideeffect "movseq r0, #0\0A", ""()
22 tail call void asm sideeffect "movseq r0, #0\0A", ""()
23 tail call void asm sideeffect "movseq r0, #0\0A", ""()
[all …]
H A Dipra.ll47 tail call void @leaf()
63 tail call void @leaf_r3()
78 tail call void @leaf()
91 tail call void @leaf_r4()
107 tail call void @leaf()
125 tail call void @leaf()
139 tail call void @leaf_s0()
155 tail call void @leaf()
169 tail call void @leaf_d0()
185 tail call void @leaf_d0()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dtail-calls.ll8 ; CHECK: tail callee_tail
21 ; CHECK: tail memcpy
32 ; CHECK: tail memcpy
57 tail call void %callee()
94 ; CHECK-NOT: tail callee_args
132 ; CHECK-NOT: tail callee_irq
141 ; we want to reuse during a tail call. Do not tail call optimize functions with
196 ; CHECK: tail test2
197 ; CHECK: tail test
198 ; CHECK: tail test1
[all …]
H A Dsaverestore.ll17 ; RV32I-NOT: tail __riscv_restore
21 ; RV64I-NOT: tail __riscv_restore
46 ; RV32I-NOT: tail __riscv_restore
50 ; RV64I-NOT: tail __riscv_restore
75 ; RV32I-NOT: tail __riscv_restore
79 ; RV64I-NOT: tail __riscv_restore
107 ; RV32I-NOT: tail __riscv_restore
147 ; RV32I: tail tail_callee
152 ; RV64I: tail tail_callee
157 ; RV32I-SR: tail tail_callee
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dderef-alloc-fns.ll26 %call = tail call noalias i8* @malloc(i64 %n)
35 %call = tail call noalias i8* @malloc(i64 40)
160 %call = tail call noalias i8* @malloc(i64 0)
223 %call = tail call noalias i8* @calloc(i64 0, i64 0)
251 %call = tail call noalias i8* @calloc(i64 0, i64 1)
260 %call = tail call noalias i8* @calloc(i64 1, i64 0)
287 %call = tail call i8* @_Znam(i64 %n)
296 %call = tail call i8* @_Znam(i64 40)
305 %call = tail call i8* @_Znwm(i64 40)
314 %call = tail call i8* @_Znam(i64 0)
[all …]
H A Dpowi.ll18 %r = tail call double @llvm.powi.f64.i32(double %fneg, i32 4)
29 %f = tail call double @llvm.fabs.f64(double %x)
30 %r = tail call double @llvm.powi.f64.i32(double %f, i32 4)
42 %r = tail call double @llvm.powi.f64.i32(double %cs, i32 4)
67 %f = tail call double @llvm.fabs.f64(double %x)
116 ; CHECK-NEXT: tail call void @use(double [[POW]])
122 tail call void @use(double %pow)
204 ; CHECK-NEXT: tail call void @use(double [[P1]])
211 tail call void @use(double %p1)
221 ; CHECK-NEXT: tail call void @use(double [[P1]])
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dreg-scavengebug.ll31 %v7 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 32768)
32 %v8 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 2147450879)
41 %v14 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v12, <16 x i32> undef)
51 %v21 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v18, <16 x i32> %v19)
55 %v25 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v14, <16 x i32> %v22)
56 %v26 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v25, <16 x i32> %v23)
57 %v27 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v26, <16 x i32> %v24)
59 %v29 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v27, <16 x i32> %v11)
64 %v34 = tail call <16 x i32> @llvm.hexagon.V6.vshuffb(<16 x i32> %v33)
85 %v54 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v35)
[all …]
H A Deliminate-pred-spill.ll50 %20 = tail call <128 x i1> @llvm.hexagon.V6.vgtb.128B(<32 x i32> %2, <32 x i32> %11)
55 %25 = tail call <128 x i1> @llvm.hexagon.V6.vgtb.128B(<32 x i32> %7, <32 x i32> %15)
62 %32 = tail call <128 x i1> @llvm.hexagon.V6.vgtb.128B(<32 x i32> %4, <32 x i32> %13)
75 %45 = tail call <128 x i1> @llvm.hexagon.V6.vgtb.128B(<32 x i32> %21, <32 x i32> %26)
82 %52 = tail call <128 x i1> @llvm.hexagon.V6.vgtb.128B(<32 x i32> %22, <32 x i32> %27)
87 %57 = tail call <128 x i1> @llvm.hexagon.V6.vgtb.128B(<32 x i32> %33, <32 x i32> %39)
92 %62 = tail call <128 x i1> @llvm.hexagon.V6.vgtb.128B(<32 x i32> %34, <32 x i32> %40)
95 %65 = tail call <128 x i1> @llvm.hexagon.V6.vgtb.128B(<32 x i32> %46, <32 x i32> %58)
99 %69 = tail call <128 x i1> @llvm.hexagon.V6.vgtb.128B(<32 x i32> %47, <32 x i32> %59)
103 %73 = tail call <128 x i1> @llvm.hexagon.V6.vgtb.128B(<32 x i32> %54, <32 x i32> undef)
[all …]
H A Dv6vect-dbl-spill.ll9 %v0 = tail call <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32 16843009)
10 %v1 = tail call <32 x i32> @llvm.hexagon.V6.vshuffh.128B(<32 x i32> undef)
11 %v2 = tail call <32 x i32> @llvm.hexagon.V6.vshuffh.128B(<32 x i32> zeroinitializer)
19 %v7 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffub.128B(<32 x i32> undef, <32 x i32> undef)
20 %v8 = tail call <128 x i1> @llvm.hexagon.V6.vgtub.128B(<32 x i32> %v7, <32 x i32> zeroinitializer)
24 %v12 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffub.128B(<32 x i32> %v10, <32 x i32> undef)
36 %v24 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %v23, <32 x i32> %v22)
44 %v32 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %v31, <32 x i32> undef)
83 %v71 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v63)
84 %v72 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v70)
[all …]
H A Dv6vect-spill-kill.ll10 %v0 = tail call <32 x i32> @llvm.hexagon.V6.vshuffh.128B(<32 x i32> undef)
31 %v15 = tail call <128 x i1> @llvm.hexagon.V6.vgtub.128B(<32 x i32> %v12, <32 x i32> undef)
32 %v16 = tail call <128 x i1> @llvm.hexagon.V6.vgtub.128B(<32 x i32> %v13, <32 x i32> undef)
41 %v25 = tail call <128 x i1> @llvm.hexagon.V6.vgtub.128B(<32 x i32> %v24, <32 x i32> undef)
58 %v42 = tail call <128 x i1> @llvm.hexagon.V6.vgtub.128B(<32 x i32> %v39, <32 x i32> undef)
59 %v43 = tail call <128 x i1> @llvm.hexagon.V6.vgtub.128B(<32 x i32> %v40, <32 x i32> undef)
60 %v44 = tail call <128 x i1> @llvm.hexagon.V6.vgtub.128B(<32 x i32> %v41, <32 x i32> undef)
80 %v64 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v62)
82 %v66 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v63)
83 %v67 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v63)
[all …]
H A Dreg-scavengebug-4.ll50 %v30 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %v29)
53 %v33 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v31)
55 %v35 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v32)
61 %v41 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v39)
62 %v42 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v40)
74 %v54 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v52)
75 %v55 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v53)
83 %v63 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %v62)
86 %v66 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v64)
88 %v68 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v65)
[all …]
H A Dexpand-vstorerw-undef2.ll40 %v3 = tail call i8* @halide_malloc()
42 %v5 = tail call i8* @halide_malloc()
44 %v7 = tail call i8* @halide_malloc()
46 %v9 = tail call i8* @halide_malloc()
72 %v23 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v22)
74 tail call void @halide_free() #3
84 %v31 = tail call <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32 1) #2
114 %v57 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v56)
116 %v59 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v56)
133 %v76 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v75)
[all …]
H A Dv6-spill1.ll7 %v0 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %a3)
8 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v0)
9 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 16843009)
10 %v3 = tail call <16 x i32> @llvm.hexagon.V6.vd0()
107 %v88 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v86)
108 %v89 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v86)
111 %v92 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v90)
114 %v94 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v90)
117 %v96 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v91)
120 %v98 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v91)
[all …]
H A Dv60-vecpred-spill.ll11 %v0 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %a3)
12 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v0)
13 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 16843009)
14 %v3 = tail call <16 x i32> @llvm.hexagon.V6.vsubw(<16 x i32> undef, <16 x i32> undef)
111 %v88 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v86)
112 %v89 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v86)
114 %v91 = tail call <32 x i32> @llvm.hexagon.V6.vunpackub(<16 x i32> %v85)
115 %v92 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v90)
118 %v94 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v90)
121 %v96 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v91)
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/AArch64/
H A Dsve-intrinsic-opts-cmpne.ll10 %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
15 %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
25 %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
30 %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
40 %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
45 %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
60 %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
74 %4 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 0)
84 %1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
99 %1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
[all …]

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