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/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dlea-dagdag.ll18 ret i16 %t6
34 ret i16 %t6
49 ret i32 %t6
64 ret i32 %t6
79 ret i32 %t6
94 ret i32 %t6
108 ret i64 %t6
122 ret i64 %t6
136 ret i64 %t6
150 ret i64 %t6
[all …]
H A Dmasked-iv-safe.ll42 %t7 = load double, ptr %t6
44 store double %t8, ptr %t6
88 %t7 = load double, ptr %t6
90 store double %t8, ptr %t6
136 %t7 = load double, ptr %t6
138 store double %t8, ptr %t6
184 %t7 = load double, ptr %t6
186 store double %t8, ptr %t6
236 store double %t8, ptr %t6
290 store double %t8, ptr %t6
[all …]
H A Dmasked-iv-unsafe.ll49 %t7 = load double, ptr %t6
51 store double %t8, ptr %t6
103 %t7 = load double, ptr %t6
105 store double %t8, ptr %t6
163 %t7 = load double, ptr %t6
165 store double %t8, ptr %t6
223 %t7 = load double, ptr %t6
225 store double %t8, ptr %t6
279 store double %t8, ptr %t6
506 %t7 = load double, ptr %t6
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dumulo-128-legalisation-lowering.ll33 ; RISCV32-NEXT: mul t6, t3, a2
34 ; RISCV32-NEXT: add s0, t6, t5
40 ; RISCV32-NEXT: sltu t6, s0, t6
44 ; RISCV32-NEXT: add s0, t4, t6
54 ; RISCV32-NEXT: add t6, t5, t4
55 ; RISCV32-NEXT: add t4, t6, s2
75 ; RISCV32-NEXT: sltu t5, t6, t5
76 ; RISCV32-NEXT: snez t6, a2
78 ; RISCV32-NEXT: and t6, s0, t6
81 ; RISCV32-NEXT: or t6, t6, s0
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dbroadcast.ll13 %t6 = insertelement <4 x float> %t5, float %arg, i32 3
14 ret <4 x float> %t6
26 %t6 = insertelement <4 x float> %t5, float %arg, i32 3
27 ret <4 x float> %t6
40 ret <4 x float> %t6
54 %t7 = fadd <4 x float> %t6, %t6
87 ret <4 x float> %t6
101 ret <4 x float> %t6
116 ret <4 x float> %t6
143 %t7 = fadd <4 x float> %t6, %t4
[all …]
H A Dbroadcast-inseltpoison.ll13 %t6 = insertelement <4 x float> %t5, float %arg, i32 3
14 ret <4 x float> %t6
26 %t6 = insertelement <4 x float> %t5, float %arg, i32 3
27 ret <4 x float> %t6
40 ret <4 x float> %t6
54 %t7 = fadd <4 x float> %t6, %t6
87 ret <4 x float> %t6
101 ret <4 x float> %t6
116 ret <4 x float> %t6
143 %t7 = fadd <4 x float> %t6, %t4
[all …]
H A Dsigned-comparison.ll12 %t6 = icmp slt i32 %t5, 500
13 ret i1 %t6
22 %t6 = icmp slt <4 x i32> %t5, <i32 500, i32 0, i32 501, i32 65535>
23 ret <4 x i1> %t6
H A Dpartally-redundant-left-shift-input-masking-after-truncation-variant-d.ll44 %t6 = shl i32 %t5, %t3 ; shift is smaller than mask
45 ret i32 %t6
81 ret <8 x i32> %t6
112 ret <8 x i32> %t6
143 ret <8 x i32> %t6
177 %t6 = shl i32 %t5, %t3 ; shift is smaller than mask
178 ret i32 %t6
211 ret i32 %t6
246 ret i32 %t6
264 %t6 = shl i32 %t5, %t3
[all …]
H A Dand-xor-merge.ll12 %t6 = and i32 %z, %y
13 %t7 = xor i32 %t3, %t6
24 %t6 = or i32 %y, %x
25 %t7 = xor i32 %t3, %t6
H A Dpartally-redundant-left-shift-input-masking-after-truncation-variant-a.ll47 %t6 = trunc i64 %t5 to i32
48 %t7 = shl i32 %t6, %t4
88 %t7 = shl <8 x i32> %t6, %t4
196 %t6 = trunc i64 %t5 to i32
197 %t7 = shl i32 %t6, %t4
231 %t6 = trunc i64 %t5 to i32
232 call void @use32(i32 %t6)
233 %t7 = shl i32 %t6, %t4
269 %t6 = trunc i64 %t5 to i32
270 call void @use32(i32 %t6)
[all …]
H A Dpartally-redundant-left-shift-input-masking-after-truncation-variant-b.ll47 %t6 = trunc i64 %t5 to i32
48 %t7 = shl i32 %t6, %t4
194 %t6 = trunc i64 %t5 to i32
195 %t7 = shl i32 %t6, %t4
233 %t6 = trunc i64 %t5 to i32
234 %t7 = shl i32 %t6, %t4
268 %t6 = trunc i64 %t5 to i32
269 call void @use32(i32 %t6)
270 %t7 = shl i32 %t6, %t4
307 call void @use32(i32 %t6)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dmidpoint-int.ll29 %t7 = sub i32 %t6, %t5
52 %t7 = sub i32 %t6, %t5
79 %t7 = sub i32 %t6, %t5
104 %t7 = sub i32 %t6, %t5
131 %t7 = sub i32 %t6, %t5
160 %t7 = sub i64 %t6, %t5
183 %t7 = sub i64 %t6, %t5
210 %t7 = sub i64 %t6, %t5
235 %t7 = sub i64 %t6, %t5
426 %t7 = sub i8 %t6, %t5
[all …]
/llvm-project-15.0.7/llvm/test/MC/LoongArch/Basic/Integer/
H A Dcrc.s12 # CHECK-ASM-AND-OBJ: crc.w.h.w $s8, $a6, $t6
14 crc.w.h.w $s8, $a6, $t6
24 # CHECK-ASM-AND-OBJ: crcc.w.b.w $t3, $t6, $sp
26 crcc.w.b.w $t3, $t6, $sp
28 # CHECK-ASM-AND-OBJ: crcc.w.h.w $r21, $s6, $t6
30 crcc.w.h.w $r21, $s6, $t6
H A Dmemory.s20 # CHECK-ASM-AND-OBJ: ld.h $a3, $t6, 80
22 ld.h $a3, $t6, 80
24 # CHECK-ASM-AND-OBJ: ld.w $t6, $s3, 92
26 ld.w $t6, $s3, 92
32 # CHECK-ASM-AND-OBJ: ld.hu $t6, $s6, 198
34 ld.hu $t6, $s6, 198
63 # CHECK: ld.d $t6, $t8, 159
65 ld.d $t6, $t8, 159
83 # CHECK64-ASM-AND-OBJ: ldx.d $t6, $s0, $t8
85 ldx.d $t6, $s0, $t8
/llvm-project-15.0.7/llvm/test/MC/COFF/
H A Dcross-section-relative.s49 .globl t6 # @t6
51 t6: label
55 .long g3-(t6+16)
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Dpseudo-jump.s12 # INSTR: auipc t6, 0
13 # INSTR: jr t6
26 # INSTR: auipc t6, 0
27 # INSTR: jr t6
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/vect/
H A Dvect-bool-basic-compile.ll20 %t6 = zext i8 %t5 to i32
21 ret i32 %t6
32 %t6 = insertelement <4 x i1> %t5, i1 %t2, i32 2
33 %t7 = insertelement <4 x i1> %t6, i1 %t3, i32 3
48 %t6 = trunc i32 %a6 to i1
57 %te = insertelement <8 x i1> %td, i1 %t6, i32 6
/llvm-project-15.0.7/llvm/test/tools/llvm-profgen/
H A Dcs-extbinary.test11 ; RUN: llvm-profdata merge --sample --text --output=%t6 %t5
12 ; RUN: FileCheck %S/recursion-compression-pseudoprobe.test --input-file %t6
13 ; RUN: llvm-profdata merge --sample --extbinary --output=%t7 %t6 && llvm-profdata merge --sample --…
14 ; RUN: diff -b %t6 %t8
/llvm-project-15.0.7/lldb/test/API/functionalities/data-formatter/data-formatter-objc/cmtime/
H A Dmain.m13 CMTime t6 = CMTimeMake(10, 1);
14 t6.flags = kCMTimeFlags_NegativeInfinity;
23 CMTimeShow(t6);
/llvm-project-15.0.7/llvm/test/Transforms/IndVarSimplify/
H A Deliminate-rem.ll19 %t6 = phi i64 [ %t9, %bb5 ], [ 0, %bb4 ] ; <i64> [#uses=2]
20 %t7 = srem i64 %t6, %arg ; <i64> [#uses=1]
23 %t9 = add nsw i64 %t6, 1 ; <i64> [#uses=2]
50 %t6 = phi i64 [ %t51, %bb49 ], [ 0, %bb4 ] ; <i64> [#uses=4]
52 %t8 = add nsw i64 %t6, %arg1 ; <i64> [#uses=1]
56 %t12 = add nsw i64 %t6, 1 ; <i64> [#uses=1]
76 %t24 = mul i64 %t6, %arg1 ; <i64> [#uses=1]
111 %t51 = add nsw i64 %t6, 1 ; <i64> [#uses=2]
/llvm-project-15.0.7/lld/test/ELF/
H A Dmap-file.s8 # RUN: echo '.global hey; hey: ret' | llvm-mc -filetype=obj -triple=x86_64 - -o %t6.o
13 # RUN: rm -f %t6.a
14 # RUN: llvm-ar rcT %t6.a %t6.o
15 # RUN: ld.lld %t1.o %t2.o %t3.o %t4.a %t5.so %t6.a -o %t -M | FileCheck --match-full-lines --strict…
16 # RUN: ld.lld %t1.o %t2.o %t3.o %t4.a %t5.so %t6.a -o %t --print-map | FileCheck --match-full-lines…
17 # RUN: ld.lld %t1.o %t2.o %t3.o %t4.a %t5.so %t6.a -o %t -Map=%t.map
21 # RUN: not ld.lld %t1.o %t2.o %t3.o %t4.a %t5.so %t6.a %t7.o -o /dev/null -M | FileCheck --strict-w…
/llvm-project-15.0.7/llvm/test/Transforms/LoopStrengthReduce/
H A Duglygep-address-space.ll3 ; LSR shouldn't consider %t8 to be an interesting user of %t6, and it
39 ; CHECK-NEXT: %t6 = load float addrspace(1)*, float addrspace(1)* addrspace(1)* %ptr.float
41 ; CHECK-NEXT: [[SCEVGEP1:%[^ ]+]] = getelementptr float, float addrspace(1)* %t6, i16 4
50 %t6 = load float addrspace(1)*, float addrspace(1)* addrspace(1)* %ptr.float
51 %t8 = bitcast float addrspace(1)* %t6 to i8 addrspace(1)* ; <i8*> [#uses=1]
/llvm-project-15.0.7/clang/test/SemaCUDA/
H A Dasm_delayed_diags.cu62 static __device__ __host__ void t6(__m256i *p) { in t6() function
79 t6(0); in m()
94 t6(0); in main()
/llvm-project-15.0.7/cross-project-tests/debuginfo-tests/clang_llvm_roundtrip/
H A Dsimplified_template_names.cpp66 struct t6 { struct
261 t6 v6; in main()
281 t6::operator new(0, 0); in main()
282 t6::operator new[](0, 0); in main()
283 t6::operator delete(nullptr, 0); in main()
284 t6::operator delete[](nullptr, 0); in main()
/llvm-project-15.0.7/lld/test/ELF/linkerscript/
H A Dassert.s29 # RUN: echo "SECTIONS { .foo : { *(.foo) ASSERT(SIZEOF(.foo) == 8, \"true\"); } }" > %t6.script
30 # RUN: ld.lld -shared -o %t6 --script %t6.script %t1.o
31 # RUN: llvm-readobj %t6 > /dev/null

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