| /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/ |
| H A D | umulo-128-legalisation-lowering.ll | 26 ; RISCV32-NEXT: add t4, t2, t1
32 ; RISCV32-NEXT: add t5, t4, t1
41 ; RISCV32-NEXT: sltu t4, t5, t4
43 ; RISCV32-NEXT: add t4, t5, t4
44 ; RISCV32-NEXT: add s0, t4, t6
45 ; RISCV32-NEXT: mul t4, t3, t0
47 ; RISCV32-NEXT: add t4, t5, t4
52 ; RISCV32-NEXT: add t4, t5, t4
57 ; RISCV32-NEXT: add t4, t4, s3
58 ; RISCV32-NEXT: add t4, s0, t4
[all …]
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| /llvm-project-15.0.7/llvm/test/Transforms/InstCombine/ |
| H A D | icmp-logical.ll | 341 %t4 = and i1 %t3, %t2
342 ret i1 %t4
353 ret i1 %t4
365 %t4 = or i1 %t3, %t2
366 ret i1 %t4
377 ret i1 %t4
424 %t5 = and i1 %t2, %t4
764 %t5 = or i1 %t2, %t4
797 %t5 = or i1 %t2, %t4
830 %t5 = or i1 %t2, %t4
[all …]
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| H A D | signed-truncation-check.ll | 48 ret i1 %t4
60 ret i1 %t4
98 ret i1 %t4
110 ret i1 %t4
123 ret i1 %t4
135 ret i1 %t4
323 ret i1 %t4
337 ret i1 %t4
351 ret i1 %t4
365 ret i1 %t4
[all …]
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| H A D | shift-amount-reassociation-with-truncation-ashr.ll | 23 %t4 = add i16 %y, -1
24 %t5 = ashr i16 %t3, %t4
110 %t4 = add i16 %y, -1
112 %t5 = ashr i16 %t3, %t4
128 %t4 = add i16 %y, -1
130 %t5 = ashr i16 %t3, %t4
150 %t4 = add i16 %y, -1
153 %t5 = ashr i16 %t3, %t4
177 %t4 = add i16 %y, -2
178 %t5 = ashr i16 %t3, %t4
[all …]
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| H A D | shift-amount-reassociation-with-truncation-lshr.ll | 23 %t4 = add i16 %y, -1
24 %t5 = lshr i16 %t3, %t4
110 %t4 = add i16 %y, -1
112 %t5 = lshr i16 %t3, %t4
128 %t4 = add i16 %y, -1
130 %t5 = lshr i16 %t3, %t4
150 %t4 = add i16 %y, -1
153 %t5 = lshr i16 %t3, %t4
177 %t4 = add i16 %y, -2
178 %t5 = lshr i16 %t3, %t4
[all …]
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| H A D | select-of-bittest.ll | 20 ret i32 %t4
35 ret <2 x i32> %t4
50 ret <2 x i32> %t4
253 ret i32 %t4
269 ret i32 %t4
500 ret i32 %t4
534 ret i32 %t4
553 ret i32 %t4
587 ret i32 %t4
621 ret i32 %t4
[all …]
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| H A D | signed-comparison.ll | 6 define i1 @scalar_zext_slt(i16 %t4) {
8 ; CHECK-NEXT: [[T6:%.*]] = icmp ult i16 %t4, 500
11 %t5 = zext i16 %t4 to i32
16 define <4 x i1> @vector_zext_slt(<4 x i16> %t4) {
18 ; CHECK-NEXT: [[T6:%.*]] = icmp ult <4 x i16> %t4, <i16 500, i16 0, i16 501, i16 -1>
21 %t5 = zext <4 x i16> %t4 to <4 x i32>
|
| H A D | shift-amount-reassociation-in-bittest-with-truncation-lshr.ll | 35 %t4 = and i32 %t1, %t3_trunc
36 %t5 = icmp ne i32 %t4, 0
56 %t5 = icmp ne i32 %t4, 0
73 %t5 = icmp ne i32 %t4, 0
96 %t5 = icmp ne i32 %t4, 0
114 %t5 = icmp ne i32 %t4, 0
131 %t5 = icmp ne i32 %t4, 0
154 %t5 = icmp ne i32 %t4, 0
266 %t5 = icmp ne i32 %t4, 0
289 %t5 = icmp ne i32 %t4, 0
[all …]
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| H A D | onehot_merge.ll | 56 %t4 = shl i32 1, %c2
59 %t5 = and i32 %t4, %k
76 %t4 = shl i32 1, %c2
79 %t5 = and i32 %t4, %k
117 %t4 = shl i32 1, %c2
120 %t5 = and i32 %t4, %k2
139 %t4 = shl i32 1, %c2
221 %t4 = shl i32 1, %c2
241 %t4 = shl i32 1, %c2
282 %t4 = shl i32 1, %c2
[all …]
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| /llvm-project-15.0.7/llvm/test/CodeGen/MSP430/ |
| H A D | bit.ll | 39 %t4 = zext i1 %t3 to i8
40 ret i8 %t4
49 %t4 = zext i1 %t3 to i8
50 ret i8 %t4
59 %t4 = zext i1 %t3 to i8
60 ret i8 %t4
70 ret i8 %t4
121 ret i16 %t4
131 ret i16 %t4
141 ret i16 %t4
[all …]
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| /llvm-project-15.0.7/llvm/test/CodeGen/X86/ |
| H A D | lea-dagdag.ll | 14 %t4 = and i8 %t1, 8
30 %t4 = and i8 %t1, 8
31 %sh = shl i8 %t4, 2
45 %t4 = and i8 %t1, 8
60 %t4 = and i8 %t1, 8
61 %sh = shl i8 %t4, 3
75 %t4 = and i16 %t1, 8
90 %t4 = and i16 %t1, 8
104 %t4 = and i8 %t1, 8
118 %t4 = and i8 %t1, 8
[all …]
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| H A D | split-store.ll | 14 %t4 = or i64 %t2, %t3
29 %t4 = or i64 %t2, %t3
45 %t4 = or i64 %t2, %t3
61 %t4 = or i64 %t2, %t3
75 %t4 = or i64 %t2, %t3
89 %t4 = or i32 %t2, %t3
103 %t4 = or i16 %t2, %t3
119 %t4 = or i64 %t2, %t3
135 %t4 = or i64 %t2, %t3
151 %t4 = or i16 %t2, %t3
[all …]
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| H A D | combine-ptest.ll | 20 ret i32 %t4
35 ret i32 %t4
53 ret i32 %t4
68 ret i32 %t4
86 ret i32 %t4
101 ret i32 %t4
119 ret i32 %t4
134 ret i32 %t4
149 ret i32 %t4
167 ret i32 %t4
[all …]
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| H A D | combine-testps.ll | 19 %t4 = icmp ne i32 %t3, 0
20 %t5 = select i1 %t4, i32 %a, i32 %b
36 %t4 = icmp ne i32 %t3, 0
37 %t5 = select i1 %t4, i32 %a, i32 %b
56 %t4 = icmp ne i32 %t3, 0
57 %t5 = select i1 %t4, i32 %a, i32 %b
73 %t4 = icmp ne i32 %t3, 0
93 %t4 = icmp ne i32 %t3, 0
110 %t4 = icmp ne i32 %t3, 0
130 %t4 = icmp ne i32 %t3, 0
[all …]
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| H A D | combine-testpd.ll | 19 %t4 = icmp ne i32 %t3, 0
20 %t5 = select i1 %t4, i32 %a, i32 %b
36 %t4 = icmp ne i32 %t3, 0
37 %t5 = select i1 %t4, i32 %a, i32 %b
56 %t4 = icmp ne i32 %t3, 0
57 %t5 = select i1 %t4, i32 %a, i32 %b
73 %t4 = icmp ne i32 %t3, 0
93 %t4 = icmp ne i32 %t3, 0
110 %t4 = icmp ne i32 %t3, 0
130 %t4 = icmp ne i32 %t3, 0
[all …]
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| /llvm-project-15.0.7/llvm/test/Transforms/Reassociate/ |
| H A D | inverses.ll | 10 %t4 = xor i32 %a, -1
11 %t5 = and i32 %t2, %t4
20 %t4 = xor <2 x i32> %a, <i32 -1, i32 undef>
21 %t5 = and <2 x i32> %t2, %t4
32 %t4 = xor i32 %a, -1
33 %t5 = and i32 %t2, %t4
45 %t4 = sub i32 0, %a
46 %t5 = add i32 %t2, %t4
58 %t4 = xor i32 %a, -1
59 %t5 = add i32 %t2, %t4
|
| /llvm-project-15.0.7/llvm/test/MC/RISCV/ |
| H A D | rv64c-aliases-valid.s | 86 # CHECK-EXPAND: lui t4, 583
87 # CHECK-EXPAND: addiw t4, t4, -1875
88 # CHECK-EXPAND: c.slli t4, 14
89 # CHECK-EXPAND: addi t4, t4, -947
90 # CHECK-EXPAND: c.slli t4, 12
91 # CHECK-EXPAND: addi t4, t4, 1511
92 # CHECK-EXPAND: c.slli t4, 13
93 # CHECK-EXPAND: addi t4, t4, -272
94 li t4, 0x123456789abcdef0
|
| /llvm-project-15.0.7/llvm/test/Transforms/NaryReassociate/ |
| H A D | pr24301.ll | 5 define i32 @foo(i32 %t4) {
14 %t5 = add i32 %t4, 8
15 %t13 = add i32 %t4, -128 ; deleted
17 %t21 = add i32 119, %t4
24 define i32 @foo2(i32 %t4) {
34 %t5 = add i32 %t4, 8 ; initially dead
35 %t13 = add i32 %t4, -128
37 %t21 = add i32 119, %t4 ; => dead after reassociation
|
| /llvm-project-15.0.7/clang/test/CXX/except/except.spec/ |
| H A D | p5-pointers.cpp | 48 void (*t4)() throw(A) = &s1; // valid in fnptrs()
49 t4 = &s3; // valid in fnptrs()
50 t4 = &s4; // valid in fnptrs()
51 t4 = &s5; // expected-error {{not superset}} in fnptrs()
59 t6 = t4; // expected-error {{not superset}} in fnptrs()
60 t4 = t6; // valid in fnptrs()
|
| /llvm-project-15.0.7/llvm/test/MC/LoongArch/Basic/Integer/ |
| H A D | atomic.s | 56 # CHECK64-ASM-AND-OBJ: amor.w $a2, $t4, $s0
58 amor.w $a2, $t4, $s0
60 # CHECK64-ASM-AND-OBJ: amor.d $sp, $t4, $s1
62 amor.d $sp, $t4, $s1
92 # CHECK64-ASM-AND-OBJ: ammax.du $a2, $t4, $s2
94 ammax.du $a2, $t4, $s2
102 ammin.du $a3, $t4, $s2
130 amor_db.w $a2, $t4, $s0
134 amor_db.d $sp, $t4, $s1
166 ammax_db.du $a2, $t4, $s2
[all …]
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| /llvm-project-15.0.7/lld/test/ELF/lto/ |
| H A D | thinlto-obj-path.ll | 7 ; RUN: rm -f %t4.o
8 ; RUN: ld.lld --plugin-opt=thinlto-index-only --plugin-opt=obj-path=%t4.o -shared %t1.o %t2.o -o /d…
9 ; RUN: llvm-readobj -h %t4.o | FileCheck %s
10 ; RUN: llvm-nm %t4.o 2>&1 | count 0
13 ; RUN: rm -f %t4.o
14 ; RUN: ld.lld --thinlto-index-only --lto-obj-path=%t4.o -shared %t1.o %t2.o -o /dev/null
15 ; RUN: llvm-readobj -h %t4.o | FileCheck %s
19 ; RUN: ld.lld --plugin-opt=obj-path=%t4.o -shared %t1.o %t2.o -o %t.dir/objpath/a.out --save-temps
|
| /llvm-project-15.0.7/llvm/test/Transforms/LoopStrengthReduce/ |
| H A D | uglygep-address-space.ll | 20 %t = add i16 %t4, 1 ; <i16> [#uses=1]
24 %t4 = phi i16 [ %t, %bb2 ], [ 0, %bb ] ; <i16> [#uses=3]
28 ; CHECK-NEXT: %t7 = icmp eq i16 %t4, 0
30 ; CHECK-NEXT: [[SCEVGEP:%[^ ]+]] = getelementptr i8, i8 addrspace(1)* %ptr.i8, i16 %t4
33 %t7 = icmp eq i16 %t4, 0 ; <i1> [#uses=1]
34 %t3 = add i16 %t4, 16 ; <i16> [#uses=1]
43 ; Use the induction variable (%t4) to access the right element
44 ; CHECK-NEXT: [[ADDRESS:%[^ ]+]] = getelementptr i8, i8 addrspace(1)* [[SCEVGEP2]], i16 %t4
48 %t2 = getelementptr inbounds i8, i8 addrspace(1)* %ptr.i8, i16 %t4 ; <i8*> [#uses=1]
|
| /llvm-project-15.0.7/flang/test/Semantics/ |
| H A D | structconst03.f90 | 40 type :: t4(k) type
43 type(t4(k)), allocatable :: link
44 end type t4
57 type(t4(0)) :: x4
84 x4 = t4(0)(modulevar4)
91 type(t4(0)) :: x4a
119 x4a = t4(0)(modulevar4)
144 type(t4(0)) :: x4
164 x4 = t4(0)(modulevar4)
|
| H A D | structconst04.f90 | 36 type :: t4 type
38 type(t4), allocatable :: link
39 end type t4
52 type(t4) :: x4
79 x4 = t4(modulevar4)
86 type(t4) :: x4a
114 x4a = t4(modulevar4)
138 type(t4) :: x4
158 x4 = t4(modulevar4)
|
| /llvm-project-15.0.7/llvm/test/CodeGen/X86/avx512-shuffles/ |
| H A D | shuffle-blend.ll | 31 ret <16 x i32> %t4
45 ret <8 x i32> %t4
59 ret <4 x i32> %t4
73 ret <2 x i32> %t4
111 ret <64 x i8> %t4
125 ret <32 x i8> %t4
138 ret <16 x i8> %t4
151 ret <8 x i8> %t4
181 ret <32 x i16> %t4
235 ret <8 x i32> %t4
[all …]
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