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/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A D2007-12-18-AddSelCmpSub.ll15 %t12 = add i32 %smax, %a
16 %t13 = add i32 %t12, 1
30 %t12 = add i32 %smax, %a
31 ret i32 %t12
43 %t12 = add i32 %smax, %a
44 ret i32 %t12
H A D2009-07-02-MaskedIntVector.ll7 …%t12 = shufflevector <16 x i8> %0, <16 x i8> zeroinitializer, <16 x i32> <i32 0, i32 16, i32 0, i3…
8 %t11 = bitcast <16 x i8> %t12 to <2 x i64> ; <<2 x i64>> [#uses=1]
H A D2010-11-01-lshr-mask.ll55 %t12 = xor i8 %t11, %t9
56 ret i8 %t12
/llvm-project-15.0.7/llvm/test/Transforms/PhaseOrdering/X86/
H A Dpr52253.ll17 %t12 = icmp eq i8 %t11, 0
18 %t14 = zext i1 %t12 to i32
33 %t12 = icmp eq i8 %t11, 0
34 %t14 = zext i1 %t12 to i8
49 %t12 = icmp eq i8 %t11, 0
51 %t14 = select i1 %t12, i32 1, i32 0
/llvm-project-15.0.7/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/
H A Dx86_isel.ll.expected37 ; PIC-NEXT: t12: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t11, t11:1
47 ; WIN-NEXT: t12: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t11, t11:1
65 ; PIC-NEXT: t12: ch,glue = CopyToReg t0, Register:i64 $rax, t9
66 ; PIC-NEXT: t13: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t12, t12:1
77 ; WIN-NEXT: t12: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t11, t11:1
95 ; PIC-NEXT: t12: ch,glue = CopyToReg t0, Register:i64 $rax, t9
96 ; PIC-NEXT: t13: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t12, t12:1
107 ; WIN-NEXT: t12: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t11, t11:1
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-fixed-length-frame-offests.ll14 ; CHECK-NEXT: t12: nxv2i1 = PTRUE_D TargetConstant:i32<31>
16 ; CHECK-NEXT: t18: nxv2i64,ch = LD1D_IMM<Mem:(volatile load (s512) from %ir.a)> t12, t2, TargetC…
18 ; CHECK-NEXT: t17: ch = ST1D_IMM<Mem:(volatile store (s512) into %ir.r0)> t18, t12, TargetFrameI…
19 ; CHECK-NEXT: t16: ch = ST1D_IMM<Mem:(volatile store (s512) into %ir.r1)> t18, t12, t8, TargetCo…
/llvm-project-15.0.7/llvm/test/Transforms/SCCP/
H A Dpr52253.ll20 %t12 = icmp eq i8 %t11, 0
21 %t14 = zext i1 %t12 to i32
44 %t12 = icmp eq i8 %t11, 0
45 %t14 = zext i1 %t12 to i8
71 %t12 = icmp eq i8 %t11, 0
73 %t14 = select i1 %t12, i32 1, i32 0
/llvm-project-15.0.7/llvm/test/Transforms/Reassociate/
H A Dmightymul.ll17 %t12 = mul i32 %t11, %t11
18 %t13 = mul i32 %t12, %t12
H A Dfast-mightymul.ll17 %t12 = fmul fast float %t11, %t11
18 %t13 = fmul fast float %t12, %t12
H A D2012-05-08-UndefLeak.ll24 %t12 = add i64 %x0, 13
42 %t30 = add i64 %t29, %t12
59 %t47 = add i64 %t46, %t12
/llvm-project-15.0.7/compiler-rt/test/asan/TestCases/Posix/
H A Dstack-overflow.cpp39 int t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13; in recursive_func()
52 t12 = z12; in recursive_func()
67 z12 = t12; in recursive_func()
/llvm-project-15.0.7/clang/test/CodeGen/
H A Darm-aapcs-zerolength-bitfield.c113 struct t12 struct
121 static int arr12_offset[(offsetof(struct t12, bar) == 8) ? 0 : -1]; argument
122 static int arr12_sizeof[(sizeof(struct t12) == 16) ? 0 : -1];
H A Darm-apcs-zerolength-bitfield.c117 struct t12 struct
125 static int arr12_offset[(offsetof(struct t12, bar) == 4) ? 0 : -1]; argument
126 static int arr12_sizeof[(sizeof(struct t12) == 8) ? 0 : -1];
H A Dms_struct-bitfield.c167 } ATTR t12; variable
168 int s12 = sizeof(t12);
H A Dcmse-clear-return.c193 T12 t12; variable
194 __attribute__((cmse_nonsecure_entry)) T12 f12(void) { return t12; } in f12()
/llvm-project-15.0.7/clang/test/CodeGenCXX/
H A Daarch64-aapcs-zerolength-bitfield.cpp114 struct t12 struct
122 static_assert(offsetof(struct t12, bar) == 8); argument
123 static_assert(sizeof(struct t12) == 16);
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dcombined-stores-chains.ll37 %t12 = bitcast i8* %v1 to i64*
44 %t142 = getelementptr inbounds i64, i64* %t12, i64 8
45 %t182 = getelementptr inbounds i64, i64* %t12, i64 9
46 %t222 = getelementptr inbounds i64, i64* %t12, i64 10
47 %t262 = getelementptr inbounds i64, i64* %t12, i64 11
H A Droot-trunc-extract-reuse.ll37 %t12 = insertelement <2 x i32> zeroinitializer, i32 %bf.load.off44, i64 0
38 %t13 = and <2 x i32> %t12, zeroinitializer
/llvm-project-15.0.7/llvm/test/Transforms/CodeGenPrepare/ARM/
H A Ddead-gep.ll13 %t12 = getelementptr inbounds %struct, %struct* %t0, i32 1, i32 500
14 %t13 = load i32, i32* %t12, align 4
/llvm-project-15.0.7/flang/test/Fir/
H A Darray-coor.fir21 // CHECK: %[[t12:.*]] = load double, ptr %[[t11]]
22 // CHECK: ret double %[[t12]]
/llvm-project-15.0.7/llvm/test/Transforms/JumpThreading/
H A Dpr33917.ll45 %t12 = zext i1 %t11 to i64
46 %cond = icmp eq i64 %t12, 1
/llvm-project-15.0.7/llvm/test/Transforms/Inline/
H A Dalloca-bonus.ll77 %t12 = add i32 %t11, 1
78 %t13 = add i32 %t12, 1
119 %t12 = add i32 %t11, 1
120 %t13 = add i32 %t12, 1
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dcallbr-asm-bb-exports.ll12 ; CHECK-NEXT: t12: ch = CopyToReg t0, Register:i32 %0, t10
16 ; CHECK-NEXT: t17: ch = TokenFactor t12, t15
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dswift-ios.ll51 define swiftcc double @t12(double %a, double %b) {
53 ; CHECK-LABEL: t12:
/llvm-project-15.0.7/llvm/test/Transforms/LoopSimplify/
H A Dmerge-exits.ll71 %t12 = icmp sgt i32 %t11, %hiPart.0
72 br i1 %t12, label %bb, label %bb3
142 %t12 = icmp sgt i32 %t11, %hiPart.0
143 br i1 %t12, label %bb, label %bb3

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