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/llvm-project-15.0.7/llvm/test/MC/Mips/eva/
H A Dvalid_R6.s40 … swe $ra,255($sp) # CHECK: swe $ra, 255($sp) # encoding: [0x7f,0xbf,0x7f,0x9f]
41 … swe $ra,-256($sp) # CHECK: swe $ra, -256($sp) # encoding: [0x7f,0xbf,0x80,0x1f]
42 … swe $ra,-53($sp) # CHECK: swe $ra, -53($sp) # encoding: [0x7f,0xbf,0xe5,0x9f]
H A Dvalid_preR6.s50 … swe $ra,255($sp) # CHECK: swe $ra, 255($sp) # encoding: [0x7f,0xbf,0x7f,0x9f]
51 … swe $ra,-256($sp) # CHECK: swe $ra, -256($sp) # encoding: [0x7f,0xbf,0x80,0x1f]
52 … swe $ra,-53($sp) # CHECK: swe $ra, -53($sp) # encoding: [0x7f,0xbf,0xe5,0x9f]
H A Dinvalid.s32 swe $33, 8($4) # CHECK: :[[@LINE]]:9: error: invalid register number
33 swe $5, 8($34) # CHECK: :[[@LINE]]:15: error: invalid register number
34 swe $5, 512($4) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
35 swe $5, -513($4) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
H A Dinvalid_R6.s41 swe $33, 8($4) # CHECK: :[[@LINE]]:19: error: invalid register number
42 swe $5, 8($34) # CHECK: :[[@LINE]]:25: error: invalid register number
43 …swe $5, 512($4) # CHECK: :[[@LINE]]:23: error: expected memory with 9-bit signed offs…
44 …swe $5, -513($4) # CHECK: :[[@LINE]]:23: error: expected memory with 9-bit signed offs…
H A Dinvalid-noeva-wrong-error.s61 …swe $ra,255($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruct…
62 …swe $ra,-256($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruct…
63 …swe $ra,-53($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruct…
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/eva/
H A Dvalid_R6-eva.txt34 0x7f 0xbf 0x7f 0x9f # CHECK: swe $ra, 255($sp)
35 0x7f 0xbf 0x80 0x1f # CHECK: swe $ra, -256($sp)
36 0x7f 0xbf 0xe5 0x9f # CHECK: swe $ra, -53($sp)
H A Dvalid_preR6-eva.txt44 0x7f 0xbf 0x7f 0x9f # CHECK: swe $ra, 255($sp)
45 0x7f 0xbf 0x80 0x1f # CHECK: swe $ra, -256($sp)
46 0x7f 0xbf 0xe5 0x9f # CHECK: swe $ra, -53($sp)
/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Dmicromips32r6-eva.s34 # CHECK-EL: swe $5, 8($4) # encoding: [0xa4,0x60,0x08,0xae]
61 # CHECK-EB: swe $5, 8($4) # encoding: [0x60,0xa4,0xae,0x08]
75 swe $5, 8($4)
H A Dmicromips-eva.s42 # CHECK-EL: swe $5, 8($4) # encoding: [0xa4,0x60,0x08,0xae]
77 # CHECK-EB: swe $5, 8($4) # encoding: [0x60,0xa4,0xae,0x08]
95 swe $5, 8($4)
/llvm-project-15.0.7/llvm/test/MC/Mips/micromips/
H A Dinvalid.s57 swe $2, -513($gp) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
58 swe $2, 512($gp) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
59 swe $33, 8($gp) # CHECK: :[[@LINE]]:7: error: invalid register number
60 swe $2, 8($33) # CHECK: :[[@LINE]]:13: error: invalid register number
H A Dvalid.s295 swe $5, 8($4) # CHECK: swe $5, 8($4) # encoding: [0x60,0xa4,0xae,0x08] label
/llvm-project-15.0.7/llvm/test/MC/Mips/micromips32r6/
H A Dinvalid.s37 swe $33, 8($4) # CHECK: :[[@LINE]]:7: error: invalid register number
38 swe $5, 8($34) # CHECK: :[[@LINE]]:13: error: invalid register number
39 swe $5, 512($4) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
185 swe $5, -513($4) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsEVAInstrInfo.td86 class SWE_DESC : STORE_EVA_DESC_BASE<"swe", GPR32Opnd, II_SWE>;
H A DMicroMipsInstrInfo.td841 def SWE_MM : MMRel, StoreMemory<"swe", GPR32Opnd, mem_simm9, null_frag,
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dmicromips-eva.mir208 # CHECK: 60 22 ae 0c swe $1, 12($2)
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/micromips32r3/
H A Dvalid-el.txt201 0xa4 0x60 0x08 0xae # CHECK: swe $5, 8($4)
H A Dvalid.txt201 0x60 0xa4 0xae 0x08 # CHECK: swe $5, 8($4)
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/micromips32r6/
H A Dvalid.txt126 0x60 0xa4 0xae 0x08 # CHECK: swe $5, 8($4)