| /llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/X86/ |
| H A D | switch_to_lookup_table.ll | 69 …val.0 = phi i32 [ 15, %sw.default ], [ 1, %sw.bb6 ], [ 62, %sw.bb5 ], [ 27, %sw.bb4 ], [ -1, %sw.b…
113 … 15, %sw.default ], [ 84, %sw.bb8 ], [ 33, %sw.bb7 ], [ 1, %sw.bb6 ], [ 62, %sw.bb5 ], [ 27, %sw.b…
147 sw.bb1: br label %sw.epilog
148 sw.bb2: br label %sw.epilog
149 sw.bb3: br label %sw.epilog
232 sw.bb1: br label %sw.epilog
233 sw.bb2: br label %sw.epilog
809 …sw.bb202 ], [ 38809, %sw.bb201 ], [ 38416, %sw.bb200 ], [ 38025, %sw.bb199 ], [ 37636, %sw.bb198 ]…
1352 …%r.0 = phi i32 [ 0, %sw.default ], [ 13, %sw.bb3 ], [ 12, %sw.bb2 ], [ 11, %sw.bb1 ], [ 10, %sw.bb…
1385 %r.0 = phi i32 [ 4, %sw.default ], [ 3, %sw.bb3 ], [ 2, %sw.bb2 ], [ 1, %sw.bb1 ], [ 0, %sw.bb ]
[all …]
|
| /llvm-project-15.0.7/llvm/test/Transforms/CodeGenPrepare/ |
| H A D | skip-merging-case-block.ll | 7 ; Expect to skip merging two empty blocks (sw.bb and sw.bb2) into sw.epilog
23 br label %sw.epilog
26 br label %sw.epilog
41 …ECK: %fp.0 = phi void (...)* [ @FD, %sw.default ], [ @F4, %sw.bb4 ], [ @F3, %sw.bb3 ], [ @F2, %sw.…
42 sw.epilog: ; preds = %sw.default, %sw.bb3, %sw.bb2, %sw.bb
43 …%fp.0 = phi void (...)* [ @FD, %sw.default ], [ @F4, %sw.bb4 ], [ @F3, %sw.bb3 ], [ @F2, %sw.bb2 ]…
83 ; CHECK: %fp.0 = phi void (...)* [ @FD, %sw.default ], [ @F4, %sw.bb4 ], [ @F3, %sw.bb3 ], [ @F2, %…
84 sw.epilog: ; preds = %sw.default, %sw.bb3, %sw.bb2, %sw.bb
85 …%fp.0 = phi void (...)* [ @FD, %sw.default ], [ @F4, %sw.bb4 ], [ @F3, %sw.bb3 ], [ @F2, %sw.bb2 ]…
127 sw.epilog: ; preds = %sw.default, %sw.bb3, %sw.bb2, %sw.bb
[all …]
|
| /llvm-project-15.0.7/llvm/test/CodeGen/WebAssembly/ |
| H A D | switch.ll | 40 i32 0, label %sw.bb
41 i32 1, label %sw.bb
42 i32 2, label %sw.bb
68 br label %sw.epilog
72 br label %sw.epilog
76 br label %sw.epilog
80 br label %sw.epilog
84 br label %sw.epilog
88 br label %sw.epilog
90 sw.epilog: ; preds = %entry, %sw.bb.5, %sw.bb.4, %sw.bb.3, %…
[all …]
|
| /llvm-project-15.0.7/llvm/test/CodeGen/ARM/ |
| H A D | 2011-08-25-ldmia_ret.ll | 20 br i1 %call, label %sw.bb18, label %sw.bb2
32 br label %sw.epilog58
46 sw.bb18:
71 sw.bb21: ; preds = %sw.bb18, %sw.bb18
79 br label %sw.epilog58
81 sw.bb33: ; preds = %sw.bb18
92 br label %sw.default56
94 sw.default56: ; preds = %sw.bb33, %land.lhs.true44, %if.then53,…
95 br label %sw.epilog58
97 sw.epilog58:
[all …]
|
| /llvm-project-15.0.7/llvm/test/Transforms/Inline/X86/ |
| H A D | switch.ll | 18 sw.default:
21 sw.bb0:
24 sw.bb1:
55 sw.bb0:
59 sw.bb1:
63 sw.bb2:
97 sw.bb101:
101 sw.bb102:
105 sw.bb103:
149 …p: ; preds = %sw.default, %sw.bb3, %sw.bb2, %sw.bb1, %sw.…
[all …]
|
| /llvm-project-15.0.7/llvm/test/Transforms/Inline/AArch64/ |
| H A D | switch.ll | 18 sw.default:
21 sw.bb0:
24 sw.bb1:
55 sw.bb0:
59 sw.bb1:
63 sw.bb2:
97 sw.bb101:
101 sw.bb102:
105 sw.bb103:
149 …p: ; preds = %sw.default, %sw.bb3, %sw.bb2, %sw.bb1, %sw.…
[all …]
|
| /llvm-project-15.0.7/llvm/test/CodeGen/X86/ |
| H A D | switch-edge-weight.ll | 20 sw.bb:
28 sw.epilog:
72 sw.bb:
76 sw.bb2:
80 sw.bb3:
84 sw.bb4:
88 sw.bb5:
133 sw.bb:
137 sw.bb2:
194 sw.bb:
[all …]
|
| /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/ |
| H A D | switch-width.ll | 27 sw.bb0:
30 sw.bb1:
37 %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
65 sw.bb0:
75 %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
114 %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
154 %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
194 %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
235 %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
274 %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
[all …]
|
| H A D | stack-store-check.ll | 40 ; CHECK-NEXT: sw s0, 596(sp)
41 ; CHECK-NEXT: sw s8, 592(sp)
42 ; CHECK-NEXT: sw s7, 588(sp)
46 ; CHECK-NEXT: sw s6, 584(sp)
52 ; CHECK-NEXT: sw s0, 548(sp)
53 ; CHECK-NEXT: sw s8, 544(sp)
54 ; CHECK-NEXT: sw s7, 540(sp)
55 ; CHECK-NEXT: sw s6, 536(sp)
56 ; CHECK-NEXT: sw s4, 564(sp)
57 ; CHECK-NEXT: sw s3, 560(sp)
[all …]
|
| /llvm-project-15.0.7/llvm/test/Examples/IRTransforms/SimplifyCFG/ |
| H A D | tut-simplify-cfg5-del-phis-for-dead-block.ll | 40 ; CHECK: sw.bb:
42 ; CHECK: sw.bb1:
44 ; CHECK: sw.bb12:
49 ; CHECK: sw.bb13:
64 i32 129, label %sw.bb
69 i32 94, label %sw.bb1
71 i32 88, label %sw.bb1
76 i32 67, label %sw.bb1
102 br label %sw.epilog24
110 sw.bb13: ; preds = %sw.bb12, %sw.bb12
[all …]
|
| /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/ |
| H A D | absol-jump-table-enabled.ll | 44 i8 1, label %sw.bb
57 br label %sw.epilog
61 br label %sw.epilog
65 br label %sw.epilog
69 br label %sw.epilog
73 br label %sw.epilog
77 br label %sw.epilog
81 br label %sw.epilog
85 br label %sw.epilog
91 sw.epilog: ; preds = %while.body, %sw.bb17, %sw.bb15, %sw.bb…
[all …]
|
| H A D | unreachable-mbb-jtreference-elimination.ll | 32 i32 1, label %sw.bb
33 i32 4, label %sw.bb
34 i32 6, label %sw.bb
35 i32 7, label %sw.bb
36 i32 9, label %sw.bb
37 i32 12, label %sw.bb
38 i32 15, label %sw.bb
39 i32 16, label %sw.bb
40 i32 24, label %sw.bb
41 i32 0, label %sw.bb26
[all …]
|
| H A D | pr22711.ll | 14 i32 17, label %sw.bb
17 i32 7, label %sw.bb3
18 i32 5, label %sw.bb4
26 br label %sw.epilog
31 br label %sw.epilog
36 br label %sw.epilog
41 br label %sw.epilog
46 br label %sw.epilog
51 br label %sw.epilog
56 br label %sw.epilog
[all …]
|
| /llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/ |
| H A D | tbb-removeadd.mir | 12 i32 0, label %sw.bb
28 sw.epilog.sink.split: ; preds = %sw.bb3, %sw.bb1, %sw.bb, %entry
29 %.sink = phi i32 [ 2, %sw.bb3 ], [ 0, %sw.bb ], [ 1, %entry ], [ 1, %sw.bb1 ]
31 br label %sw.epilog
67 blocks: [ '%bb.2.sw.bb', '%bb.3.sw.bb1', '%bb.5.sw.epilog.sink.split',
68 '%bb.6.sw.epilog', '%bb.4.sw.bb3' ]
84 …cessors: %bb.2.sw.bb(0x1c71c71c), %bb.3.sw.bb1(0x1c71c71c), %bb.5.sw.epilog.sink.split(0x1c71c71c)…
92 bb.2.sw.bb:
99 bb.3.sw.bb1:
108 bb.4.sw.bb3:
[all …]
|
| /llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/RISCV/ |
| H A D | switch_to_lookup_table-rv32.ll | 41 i32 43, label %sw.bb1
42 i32 44, label %sw.bb2
43 i32 45, label %sw.bb3
57 …val.0 = phi i32 [ 15, %sw.default ], [ 1, %sw.bb6 ], [ 62, %sw.bb5 ], [ 27, %sw.bb4 ], [ -1, %sw.b…
101 … 15, %sw.default ], [ 84, %sw.bb8 ], [ 33, %sw.bb7 ], [ 1, %sw.bb6 ], [ 62, %sw.bb5 ], [ 27, %sw.b…
135 sw.bb1: br label %sw.epilog
136 sw.bb2: br label %sw.epilog
137 sw.bb3: br label %sw.epilog
138 sw.default: br label %sw.epilog
140 sw.epilog:
[all …]
|
| H A D | switch_to_lookup_table-rv64.ll | 41 i32 43, label %sw.bb1
42 i32 44, label %sw.bb2
43 i32 45, label %sw.bb3
57 …val.0 = phi i32 [ 15, %sw.default ], [ 1, %sw.bb6 ], [ 62, %sw.bb5 ], [ 27, %sw.bb4 ], [ -1, %sw.b…
101 … 15, %sw.default ], [ 84, %sw.bb8 ], [ 33, %sw.bb7 ], [ 1, %sw.bb6 ], [ 62, %sw.bb5 ], [ 27, %sw.b…
135 sw.bb1: br label %sw.epilog
136 sw.bb2: br label %sw.epilog
137 sw.bb3: br label %sw.epilog
138 sw.default: br label %sw.epilog
140 sw.epilog:
[all …]
|
| /llvm-project-15.0.7/llvm/test/CodeGen/Mips/ |
| H A D | jtstat.ll | 13 i32 115, label %sw.bb
17 i32 99, label %sw.bb4
25 br label %sw.epilog
29 br label %sw.epilog
33 br label %sw.epilog
37 br label %sw.epilog
41 br label %sw.epilog
45 br label %sw.epilog
49 br label %sw.epilog
53 br label %sw.epilog
[all …]
|
| /llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/ |
| H A D | pic-jumptables.ll | 11 i32 1, label %sw.bb
12 i32 2, label %sw.bb1
13 i32 3, label %sw.bb2
14 i32 4, label %sw.bb3
20 br label %sw.epilog
24 br label %sw.epilog
28 br label %sw.epilog
32 br label %sw.epilog
35 br label %sw.epilog
37 sw.epilog: ; preds = %sw.bb4, %sw.bb3, %sw.bb2, %sw.bb1, %sw…
[all …]
|
| /llvm-project-15.0.7/llvm/test/Transforms/CodeGenPrepare/AArch64/ |
| H A D | widen_switch.ll | 15 sw.bb0:
18 sw.bb1:
21 sw.default:
25 %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
45 sw.bb0:
48 sw.bb1:
51 sw.default:
55 %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
76 sw.bb0:
79 sw.bb1:
[all …]
|
| /llvm-project-15.0.7/llvm/test/Transforms/CodeGenPrepare/X86/ |
| H A D | widen_switch.ll | 16 sw.bb0:
19 sw.bb1:
22 sw.default:
26 %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
47 sw.bb0:
50 sw.bb1:
53 sw.default:
57 %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
85 sw.bb0:
88 sw.bb1:
[all …]
|
| /llvm-project-15.0.7/llvm/test/Instrumentation/SanitizerCoverage/ |
| H A D | switch-tracing.ll | 13 i32 1, label %sw.bb
15 i32 101, label %sw.bb.2
20 br label %sw.epilog
24 br label %sw.epilog
28 br label %sw.epilog
30 sw.epilog: ; preds = %entry, %sw.bb.2, %sw.bb.1, %sw.bb
37 i72 1, label %sw.bb
44 br label %sw.epilog
48 br label %sw.epilog
52 br label %sw.epilog
[all …]
|
| /llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ |
| H A D | jump_table_and_brjt.mir | 33 sw.epilog: ; preds = %sw.default
41 sw.bb4: ; preds = %sw.epilog
159 bb.2.sw.bb:
163 bb.3.sw.bb1:
167 bb.4.sw.bb2:
171 bb.5.sw.bb3:
177 bb.7.sw.epilog:
191 bb.8.sw.bb4:
195 bb.9.sw.bb5:
199 bb.10.sw.bb6:
[all …]
|
| /llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/ |
| H A D | jump_table_and_brjt.mir | 33 sw.epilog: ; preds = %sw.default
41 sw.bb4: ; preds = %sw.epilog
164 bb.2.sw.bb:
168 bb.3.sw.bb1:
172 bb.4.sw.bb2:
176 bb.5.sw.bb3:
182 bb.7.sw.epilog:
199 bb.8.sw.bb4:
203 bb.9.sw.bb5:
207 bb.10.sw.bb6:
[all …]
|
| /llvm-project-15.0.7/llvm/test/Transforms/Inline/ |
| H A D | switch.ll | 18 sw.default:
21 sw.bb0:
24 sw.bb1:
27 sw.bb2:
30 sw.bb3:
33 sw.bb4:
36 sw.bb5:
39 sw.bb6:
42 sw.bb7:
45 sw.bb8:
[all …]
|
| /llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ |
| H A D | jump_table_and_brjt.ll | 213 i32 0, label %sw.bb
214 i32 4, label %sw.bb
215 i32 1, label %sw.bb1
216 i32 5, label %sw.bb1
236 br label %sw.epilog
238 sw.epilog: ; preds = %sw.default
246 sw.bb4: ; preds = %sw.epilog
249 sw.bb5: ; preds = %sw.epilog
252 sw.bb6: ; preds = %sw.epilog
255 sw.bb7: ; preds = %sw.epilog
[all …]
|