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/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Darm64-arithmetic-encoding.s88 subs w3, w4, #1024
91 subs x3, x4, #1024
148 subs w12, w13, w14
149 subs x12, x13, x14
302 subs w1, w2, w3, uxtb
303 subs w1, w2, w3, uxth
304 subs w1, w2, w3, uxtw
305 subs w1, w2, w3, uxtx
306 subs w1, w2, w3, sxtb
307 subs w1, w2, w3, sxth
[all …]
H A Dalias-addsubimm.s67 subs w0, w2, #2, lsl 12
72 subs x1, x3, #2, lsl 12
77 subs x1, x3, #4
82 subs x1, x3, #4095, lsl 0
85 subs x3, x4, #0
91 subs w0, w2, #-2, lsl 12
96 subs x1, x3, #-2, lsl 12
101 subs x1, x3, #-4
106 subs x1, x3, #-4095, lsl 0
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb/
H A Dbranchless-cmp.ll10 ; CHECK: subs r0, r0, r1
11 ; CHECK-NEXT: subs r1, r0, #1
22 ; CHECK: subs r1, r0, r1
34 ; CHECK: subs r1, r0, r1
46 ; CHECK: subs r0, r0, r1
47 ; CHECK-NEXT: subs r1, r0, #1
58 ; CHECK: subs r0, r0, r1
71 ; CHECK: subs r0, r0, r1
84 ; CHECK: subs r0, r0, r1
97 ; CHECK: subs r0, r0, r1
[all …]
/llvm-project-15.0.7/llvm/test/MC/VE/
H A DSUB.s14 # CHECK-INST: subs.w.sx %s11, 63, (60)1
16 subs.w.sx %s11, 63, (60)1
18 # CHECK-INST: subs.w.zx %s11, -64, %s22
20 subs.w.zx %s11, -64, %s22
22 # CHECK-INST: subs.l %s11, -64, (22)0
24 subs.l %s11, -64, (22)0
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dthumb_rewrites.s44 subs r0, r0, r0
45 @ CHECK: subs r0, r0, r0 @ encoding: [0x00,0x1a]
47 subs r3, r3, #5
48 @ CHECK: subs r3, r3, #5 @ encoding: [0x5b,0x1f]
50 subs r3, #5
51 @ CHECK: subs r3, #5 @ encoding: [0x05,0x3b]
53 subs r2, r2, #8
54 @ CHECK: subs r2, #8 @ encoding: [0x08,0x3a]
H A Dthumb-add-sub-width.s46 subs r0, r0, r1 // T1, T2
47 subs r0, r1 // T1, T2
54 subs r0, r0, r1 // T1, T2
55 subs r0, r1 // T1, T2
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dthumb2-sub3.ll6 ; CHECK: subs r0, #171
15 ; CHECK: subs.w r0, r0, #1179666
24 ; CHECK: subs.w r0, r0, #872428544
33 ; CHECK: subs.w r0, r0, #1448498774
42 ; CHECK: subs.w r0, r0, #66846720
51 ; CHECK: subs r0, #2
H A Dthumb2-sbc.ll5 ; CHECK: subs r0, r0, r2
13 ; CHECK: subs r0, #2
22 ; CHECK: subs r0, #2
31 ; CHECK: subs r0, #2
40 ; CHECK: subs r0, #2
49 ; CHECK: subs r0, #2
H A Dschedm7-hazard.ll14 ; CHECK-NEXT: subs r1, r3, r1
16 ; CHECK-NEXT: subs r1, r1, r2
24 ; NOBANK-NEXT: subs r1, r3, r1
25 ; NOBANK-NEXT: subs r1, r1, r2
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AArch64/
H A Darm64-arithmetic.txt78 # CHECK: subs w3, w4, #1024
80 # CHECK: subs x3, x4, #1024
151 # CHECK: subs w12, w13, w14
152 # CHECK: subs x12, x13, x14
295 # CHECK: subs w1, w2, w3, uxtb
296 # CHECK: subs w1, w2, w3, uxth
297 # CHECK: subs w1, w2, w3
321 # CHECK: subs w1, wsp, w3
322 # CHECK: subs w1, wsp, w3
349 # CHECK: subs w1, wsp, w8
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Exynos/
H A Dextended-register.s8 subs x6, x7, w8, uxtw #2
12 subs x18, x19, w20, sxtw #2
51 # EM3-NEXT: 1 1 0.25 subs x6, x7, w8, uxtw #2
55 # EM3-NEXT: 1 2 0.50 subs x18, x19, w20, sxtw #2
60 # EM4-NEXT: 1 1 0.25 subs x6, x7, w8, uxtw #2
64 # EM4-NEXT: 1 2 0.50 subs x18, x19, w20, sxtw #2
69 # EM5-NEXT: 1 1 0.25 subs x6, x7, w8, uxtw #2
73 # EM5-NEXT: 1 2 0.50 subs x18, x19, w20, sxtw #2
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dvselect_imax.ll83 ; CHECK-NEXT: subs r2, r2, lr
91 ; CHECK-NEXT: subs r2, r2, r4
99 ; CHECK-NEXT: subs r2, r5, r2
104 ; CHECK-NEXT: subs r7, r4, r7
150 ; CHECK-NEXT: subs r0, r1, r0
158 ; CHECK-NEXT: subs r1, r1, r2
167 ; CHECK-NEXT: subs r0, r2, r0
175 ; CHECK-NEXT: subs r0, r4, r0
184 ; CHECK-NEXT: subs r0, r4, r0
194 ; CHECK-NEXT: subs r0, r4, r0
[all …]
H A Dusub_sat.ll16 ; CHECK-T1-NEXT: subs r0, r0, r1
25 ; CHECK-T2-NEXT: subs r0, r0, r1
32 ; CHECK-ARM-NEXT: subs r0, r0, r1
46 ; CHECK-T1-NEXT: subs r2, r0, r2
69 ; CHECK-T2-NEXT: subs r0, r0, r2
81 ; CHECK-ARM-NEXT: subs r0, r0, r2
96 ; CHECK-T1-NEXT: subs r0, r0, r1
128 ; CHECK-T1-NEXT: subs r0, r0, r1
160 ; CHECK-T1-NEXT: subs r0, r0, r1
169 ; CHECK-T2-NEXT: subs r0, r0, r1
[all …]
H A Dlong_shift.ll10 ; CHECK-LE-NEXT: subs r0, r0, r2
18 ; CHECK-BE-NEXT: subs r1, r1, r3
32 ; CHECK-LE-NEXT: subs r1, r2, #32
39 ; CHECK-BE-NEXT: subs r1, r3, #32
53 ; CHECK-LE-NEXT: subs r2, r2, #32
63 ; CHECK-BE-NEXT: subs r2, r3, #32
78 ; CHECK-LE-NEXT: subs r2, r2, #32
88 ; CHECK-BE-NEXT: subs r2, r3, #32
H A Dssub_sat.ll19 ; CHECK-T1-NEXT: subs r0, r0, r1
69 ; CHECK-T1-NEXT: subs r5, r0, r2
94 ; CHECK-T2-NEXT: subs r0, r0, r2
109 ; CHECK-ARM-NEXT: subs r0, r0, r2
126 ; CHECK-T1-NEXT: subs r0, r0, r1
195 ; CHECK-T1-NEXT: subs r0, r0, r1
251 ; CHECK-T1-NEXT: subs r0, r0, r1
315 ; CHECK-T1-NEXT: subs r0, r0, r6
325 ; CHECK-T1-NEXT: subs r1, r1, r4
332 ; CHECK-T1-NEXT: subs r2, r2, r4
[all …]
H A Dsub.ll10 ; CHECK-LE: subs{{.*}} r0, #171
12 ; CHECK-BE: subs r1, r1, #171
21 ; CHECK-LE: subs{{.*}} r0, r0, #66846720
23 ; CHECK-BE: subs r1, r1, #66846720
32 ; CHECK-LE: subs{{.*}} r0, #2
34 ; CHECK-BE: subs r1, r1, #2
H A Dusub_sat_plus.ll17 ; CHECK-T1-NEXT: subs r0, r0, r1
27 ; CHECK-T2-NEXT: subs r0, r0, r1
35 ; CHECK-ARM-NEXT: subs r0, r0, r1
52 ; CHECK-T1-NEXT: subs r3, r0, r3
77 ; CHECK-T2-NEXT: subs r0, r0, r2
91 ; CHECK-ARM-NEXT: subs r0, r0, r2
108 ; CHECK-T1-NEXT: subs r0, r0, r1
147 ; CHECK-T1-NEXT: subs r0, r0, r1
187 ; CHECK-T1-NEXT: subs r0, r0, r2
198 ; CHECK-T2-NEXT: subs r0, r0, r1
[all …]
H A Dcmp.ll6 ; CHECK: subs r0, r0, r1
8 ; CHECK-T2: subs r0, r0, r1
20 ; CHECK-T2: subs r0, r0, r1
42 ; CHECK: subs r0, r0, r1, lsr #6
44 ; CHECK-T2: subs.w r0, r0, r1, lsr #6
67 ; CHECK: subs r0, r0, r0, ror #8
69 ; CHECK-T2: subs.w r0, r0, r0, ror #8
/llvm-project-15.0.7/llvm/test/CodeGen/VE/Scalar/
H A Dsubtraction.ll6 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
17 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
28 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
38 ; CHECK-NEXT: subs.l %s0, %s0, %s1
47 ; CHECK-NEXT: subs.l %s1, %s1, %s3
52 ; CHECK-NEXT: subs.l %s1, %s1, %s3
53 ; CHECK-NEXT: subs.l %s0, %s0, %s2
92 ; CHECK-NEXT: subs.l %s0, %s0, %s1
101 ; CHECK-NEXT: subs.l %s1, %s1, %s3
106 ; CHECK-NEXT: subs.l %s1, %s1, %s3
[all …]
H A Drem.ll22 ; CHECK-NEXT: subs.l %s0, %s0, %s1
34 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
60 ; CHECK-NEXT: subs.l %s0, %s0, %s1
72 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
85 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
101 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
158 ; CHECK-NEXT: subs.l %s0, %s0, %s1
198 ; CHECK-NEXT: subs.l %s0, %s0, %s1
240 ; CHECK-NEXT: subs.l %s0, 3, %s0
252 ; CHECK-NEXT: subs.w.sx %s0, 3, %s0
[all …]
/llvm-project-15.0.7/compiler-rt/lib/builtins/arm/
H A Daddsf3.S78 subs r6, r2, r3
85 subs r6, r6, #1
91 subs r3, r3, r6
168 subs r4, r4, r5 // aSignificand -= bSignificand;
184 subs r5, r5, #(typeWidth - significandBits - 3 - 1)
187 subs r2, r2, r5
192 subs r6, r6, r2 // 1 - aExponent;
195 subs r3, r3, r6
H A Dudivsi3.S117 subs r0, r0, #(16 * BLOCK_SIZE)
129 subs r0, r0, #(8 * BLOCK_SIZE)
141 subs r0, r0, #(4 * BLOCK_SIZE)
153 subs r0, r0, #(2 * BLOCK_SIZE)
165 subs r0, r0, #(1 * BLOCK_SIZE)
202 subs r0, r0, r2; \
/llvm-project-15.0.7/libc/AOR_v20.02/string/aarch64/
H A Dmemcmp.S32 subs limit, limit, 8
40 subs limit, limit, 8
55 subs limit, limit, 16
76 subs limit, limit, 16
128 subs limit, limit, 1
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dusub_sat.ll13 ; CHECK-NEXT: subs w8, w0, w1
23 ; CHECK-NEXT: subs x8, x0, x1
34 ; CHECK-NEXT: subs w8, w8, w1, uxth
45 ; CHECK-NEXT: subs w8, w8, w1, uxtb
57 ; CHECK-NEXT: subs w8, w9, w8
H A Darm64-early-ifcvt.ll41 ; CHECK: {{subs.*wzr,|cmp}} w2, #1
59 ; CHECK: {{subs.*xzr,|cmp}} x2, #1
77 ; CHECK: {{subs.*wzr,|cmp}} w2, #1
95 ; CHECK: {{subs.*xzr,|cmp}} x2, #1
113 ; CHECK: {{subs.*wzr,|cmp}} w2, #1
131 ; CHECK: {{subs.*xzr,|cmp}} x2, #1
149 ; CHECK: {{subs.*wzr,|cmp}} w2, #1
167 ; CHECK: {{subs.*xzr,|cmp}} x2, #1
185 ; CHECK: {{subs.*wzr,|cmp}} w2, #1
203 ; CHECK: {{subs.*xzr,|cmp}} x2, #1
[all …]

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