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Searched refs:subregs (Results 1 – 25 of 50) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVERegisterInfo.td13 class VEReg<bits<7> enc, string n, list<Register> subregs = [],
19 let SubRegs = subregs;
29 class VEVecReg<bits<8> enc, string n, list<Register> subregs = [],
35 let SubRegs = subregs;
39 class VEMaskReg<bits<4> enc, string n, list<Register> subregs = [],
45 let SubRegs = subregs;
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td35 : RegisterWithSubRegs<n, subregs> {
44 class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs>
45 : MipsRegWithSubRegs<Enc, n, subregs> {
53 class AFPR<bits<16> Enc, string n, list<Register> subregs>
54 : MipsRegWithSubRegs<Enc, n, subregs> {
59 class AFPR64<bits<16> Enc, string n, list<Register> subregs>
60 : MipsRegWithSubRegs<Enc, n, subregs> {
66 class AFPR128<bits<16> Enc, string n, list<Register> subregs>
67 : MipsRegWithSubRegs<Enc, n, subregs> {
72 class ACCReg<bits<16> Enc, string n, list<Register> subregs>
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfoMMA.td20 class ACC<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
22 let SubRegs = subregs;
29 class UACC<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
31 let SubRegs = subregs;
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFRegisterInfo.td24 class Ri<bits<16> Enc, string n, list<Register> subregs>
25 : RegisterWithSubRegs<n, subregs> {
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td29 RegisterWithSubRegs<n, subregs> {
42 RegisterWithSubRegs<n, subregs> {
63 class Rd<bits<5> num, string n, list<Register> subregs,
65 HexagonDoubleReg<num, n, subregs, alt> {
66 let SubRegs = subregs;
86 HexagonDoubleReg<num, n, subregs, alt> {
87 let SubRegs = subregs;
98 HexagonDoubleSys<num, n, subregs, alt> {
99 let SubRegs = subregs;
114 HexagonDoubleReg<num, n, subregs> {
[all …]
/llvm-project-15.0.7/llvm/test/TableGen/
H A DGlobalISelEmitterRegSequence.td6 // Boilerplate code for setting up some registers with subregs.
7 class MyReg<string n, list<Register> subregs = []>
9 let SubRegs = subregs;
H A DConcatenatedSubregs.td5 class MyReg<string n, list<Register> subregs = []>
8 let SubRegs = subregs;
100 // Check that all subregs are generated on some examples
H A Ddag-isel-subregs.td3 include "reg-with-subregs-common.td"
H A Drc-weight-override.td3 include "reg-with-subregs-common.td"
H A Dpset-enum.td4 include "reg-with-subregs-common.td"
H A Dinhibit-pset.td3 include "reg-with-subregs-common.td"
H A DGlobalISelEmitterCustomPredicate.td28 // Boilerplate code for setting up some registers with subregs.
29 class MyReg<string n, list<Register> subregs = []>
31 let SubRegs = subregs;
H A DGlobalISelEmitterSubreg.td7 // Boilerplate code for setting up some registers with subregs.
8 class MyReg<string n, list<Register> subregs = []>
10 let SubRegs = subregs;
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td12 class LanaiReg<bits<5> num, string n, list<Register> subregs = [],
17 let SubRegs = subregs;
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600RegisterInfo.td19 class R600Reg_128<string n, list<Register> subregs, bits<16> encoding> :
20 RegisterWithSubRegs<n, subregs> {
28 class R600Reg_64<string n, list<Register> subregs, bits<16> encoding> :
29 RegisterWithSubRegs<n, subregs> {
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.td21 class MSP430RegWithSubregs<bits<4> num, string n, list<Register> subregs,
23 : RegisterWithSubRegs<n, subregs> {
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td35 class Rdi<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
36 let SubRegs = subregs;
44 class Rd<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
45 let SubRegs = subregs;
51 class Rq<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
52 let SubRegs = subregs;
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dlo16-lo16-physreg-copy-sgpr.mir4 # Note: GFX8 did not allow SDWA SGPR sources. Therefor no HI16 subregs can be used there.
H A Dreserved-reg-in-clause.mir3 # Make sure we do not produce early-clobber list with odd subregs.
H A Dlo16-hi16-illegal-copy.mir6 # Note: GFX8 did not allow SDWA SGPR sources. Therefor no HI16 subregs can be used there.
/llvm-project-15.0.7/lldb/source/Plugins/ABI/X86/
H A DABIX86.cpp58 llvm::ArrayRef<RegData *> subregs, uint32_t base_size, in addPartialRegisters() argument
61 for (const RegData *subreg : subregs) { in addPartialRegisters()
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-dead-register-def-bug.ll5 ; with dead defs, but live implicit-defs of subregs:
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dlivephysregs-lane-masks2.mir39 ; A live-in register without subregs, but with a lane mask that is not ~0
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td14 class AVRReg<bits<16> num, string name, list<Register> subregs = [],
15 list<string> altNames = []> : RegisterWithSubRegs<name, subregs> {
20 let SubRegs = subregs;
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td17 class SystemZRegWithSubregs<string n, list<Register> subregs>
18 : RegisterWithSubRegs<n, subregs> {
142 // Not used directly, but needs to exist for ADDR32 and ADDR64 subregs

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