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/llvm-project-15.0.7/llvm/test/Transforms/GVNHoist/
H A Dhoist-convergent.ll23 %sub5 = fsub float %max, %a
24 %mul6 = call float @convergent_func(float %sub5, float %div)
53 %sub5 = fsub float %max, %a
54 %mul6 = call float @func(float %sub5, float %div) #0
79 %sub5 = fsub float %max, %a
80 %mul6 = call float @func(float %sub5, float %div)
H A Dhoist.ll32 %sub5 = fsub float %min, %a
33 %mul6 = fmul float %sub5, %div
81 %sub5 = fsub float %5, %4
82 %mul6 = fmul float %sub5, %div
133 %sub5 = fsub float %5, %4
180 %sub5 = fsub float %5, %4
298 %sub5 = fsub float %5, %4
373 %sub5 = fsub float %5, %4
422 %sub5 = fsub float %4, %3
463 %sub5 = fsub float %5, %4
[all …]
H A Dhoist-newgvn.ll38 %sub5 = fsub float %5, %4
39 %mul6 = fmul float %sub5, %div
83 %sub5 = fsub float %5, %4
84 %mul6 = fmul float %sub5, %div
/llvm-project-15.0.7/llvm/test/Transforms/LoopReroll/
H A Dnegative.ll17 ;CHECK-NOT: %sub5 = add nsw i32 %len.addr.014, -1
18 ;CHECK-NOT: %sub5 = add nsw i32 %len.addr.014, -2
22 %len.addr.014 = phi i32 [ %len, %while.body.lr.ph ], [ %sub5, %while.body ]
34 %sub5 = add nsw i32 %len.addr.014, -2
35 %cmp = icmp sgt i32 %sub5, 1
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dmachine-outliner-return-1.ll18 %sub5 = sub nsw i32 %call, %add1
19 %div = sdiv i32 %mul4, %sub5
42 %sub5 = sub nsw i32 %call, %add1
43 %div = sdiv i32 %mul4, %sub5
/llvm-project-15.0.7/flang/test/Semantics/OpenACC/
H A Dacc-routine-validity.f9045 subroutine sub5(a) subroutine
48 end subroutine sub5
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dstldst.ll28 %sub5 = add nsw i32 %6, -10
32 … getelementptr inbounds ([32 x i8], [32 x i8]* @.str, i32 0, i32 0), i32 %sub5, i32 %add6, i32 %0,…
33 … %1, i32 %add, i32 %add1, i32 %sub, i32 %add2, i32 %add3, i32 %sub4, i32 %sub5, i32 %add6) nounwind
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dcoalescer-subreg-join.mir60 %11.sub5 = COPY %1
69 %20.sub5 = COPY %2
H A Dexpand-si-indirect.mir46 …b2, killed %8, %subreg.sub3, killed %9, %subreg.sub4, killed %10, %subreg.sub5, killed %11, %subre…
65 %38:vgpr_32 = COPY %23.sub5
89 %58:vgpr_32 = COPY %25.sub5
H A Dsplitkit-copy-bundle.mir28 ; RA-NEXT: %2.sub5:sgpr_1024 = COPY %2.sub1
57 ; RA-NEXT: %3.sub5:sgpr_1024 = COPY %3.sub0
183 %2.sub5:sgpr_1024 = COPY %2.sub1
212 %3.sub5:sgpr_1024 = COPY %3.sub0
260 ; RA-NEXT: [[DEF2]].sub5:sgpr_512 = S_MOV_B32 -1
285 …SGPR1:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR [[DEF]], %14.sub5, 0 :: (dereferencea…
328 %2.sub5:sgpr_512 = S_MOV_B32 -1
340 …%6:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR %0:sgpr_128, %2.sub5:sgpr_512, 0 :: (dereferenceab…
H A Dsched-assert-dead-def-subreg-use-other-subreg.mir44 ; CHECK-NEXT: %11.sub5:vreg_512 = COPY undef [[V_MOV_B32_e32_]]
68 %11.sub5:vreg_512 = COPY undef %1
H A Dgreedy-liverange-priority.mir32 %16.sub5:sgpr_256 = COPY %16.sub0
97 %25.sub5:sgpr_256 = COPY %25.sub0
H A Dlimit-soft-clause-reg-pressure.mir50 … dead %15:vgpr_32 = nofpexcept V_ADD_F32_e64 0, 0, 0, %4.sub5, 0, 0, implicit $mode, implicit $exec
66 … dead %31:vgpr_32 = nofpexcept V_ADD_F32_e64 0, 0, 0, %5.sub5, 0, 0, implicit $mode, implicit $exec
82 … dead %47:vgpr_32 = nofpexcept V_ADD_F32_e64 0, 0, 0, %8.sub5, 0, 0, implicit $mode, implicit $exec
/llvm-project-15.0.7/llvm/test/TableGen/Common/
H A Dreg-with-subregs-common.td61 def GPR256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
73 def GPR512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
94 def GPR1024 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
/llvm-project-15.0.7/llvm/test/Transforms/Inline/ARM/
H A Dloop-memcpy.ll24 %sub5 = sub i32 %num, %and2
25 %shr = and i32 %sub5, -4
26 %sub7 = sub i32 %sub5, %shr
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Ddiv-shift-crash.ll68 %sub5.i.i.i.i = sub nsw i32 -701565022, %storemerge.i.i.i
69 %.sub5.i.i.i.i = select i1 %cmp.i.i.i.i, i32 -701565022, i32 %sub5.i.i.i.i
73 %div.i.i.i.i = udiv i32 %conv33.i.i.i, %.sub5.i.i.i.i
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A D2011-12-05-NoSpillDupCR.ll46 %sub5.us = sub i64 31999, %indvars.iv20
47 %sext = shl i64 %sub5.us, 32
81 %sub5.us.1 = sub i64 31999, %indvars.iv20.1
82 %sext23 = shl i64 %sub5.us.1, 32
103 %sub5.us.2 = sub i64 31999, %indvars.iv20.2
104 %sext24 = shl i64 %sub5.us.2, 32
125 %sub5.us.3 = sub i64 31999, %indvars.iv20.3
126 %sext25 = shl i64 %sub5.us.3, 32
147 %sub5.us.4 = sub i64 31999, %indvars.iv20.4
148 %sext26 = shl i64 %sub5.us.4, 32
/llvm-project-15.0.7/clang/test/Sema/
H A Dtypecheck-binop.c21 int sub5(void *P, int *Q) { in sub5() function
/llvm-project-15.0.7/flang/test/Lower/OpenMP/
H A Dcopyin.f90201 call sub5(x7)
/llvm-project-15.0.7/polly/test/ScheduleOptimizer/
H A Douter_coincidence.ll36 %sub5 = add nsw i64 %j.0, -1
39 %arrayidx7 = getelementptr inbounds float, float* %arrayidx6, i64 %sub5
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dscatter-vectorize-reorder.ll45 %sub5.i74.i = fsub float 0.000000e+00, %1
61 %add5.i.i = fadd float %sub5.i74.i, %vddir.sroa.8.0.i
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dfp-sub-02.ll113 %sub5 = fsub double %sub4, %val5
114 %sub6 = fsub double %sub5, %val6
H A Dfp-sub-01.ll113 %sub5 = fsub float %sub4, %val5
114 %sub6 = fsub float %sub5, %val6
H A Dint-sub-04.ll133 %sub5 = sub i64 %sub4, %val5
134 %sub6 = sub i64 %sub5, %val6
/llvm-project-15.0.7/polly/test/ScopInfo/
H A Daliasing_many_parameters_not_all_involved.ll42 %sub5 = sub nsw i32 %add, %tmp3
45 %add7 = add nsw i32 %sub5, %tmp4

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