sub2 (reference) in projects: llvm-project-15.0.7

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Searched refs:sub2 (Results 1 – 25 of 234) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A D	splitkit-copy-live-lanes.mir	25 ; CHECK-NEXT: %3.sub2:sgpr_128 = COPY %2.sub2 107 ; CHECK-NEXT: undef %131.sub2:vreg_128 = COPY %87.sub2 112 ; CHECK-NEXT: undef %134.sub2:vreg_128 = COPY %91.sub2 124 ; CHECK-NEXT: undef %103.sub2:vreg_128 = COPY %102.sub2 129 ; CHECK-NEXT: undef %112.sub2:vreg_128 = COPY %111.sub2 131 ; CHECK-NEXT: undef %116.sub2:vreg_128 = COPY %115.sub2 133 ; CHECK-NEXT: undef %120.sub2:vreg_128 = COPY %119.sub2 135 ; CHECK-NEXT: undef %124.sub2:vreg_128 = COPY %123.sub2 140 ; CHECK-NEXT: undef %139.sub2:vreg_128 = COPY %138.sub2 142 ; CHECK-NEXT: undef %143.sub2:vreg_128 = COPY %142.sub2 [all …]
H A D	pr51516.mir	`65 %27.sub2:vreg_128 = COPY %4.sub1 67 %26.sub0:vreg_128 = COPY %4.sub2 68 %26.sub2:vreg_128 = COPY %4.sub3 71 %25.sub2:vreg_128 = COPY %5.sub1 73 %24.sub0:vreg_128 = COPY %5.sub2 74 %24.sub2:vreg_128 = COPY %5.sub3 77 %23.sub2:vreg_128 = COPY %6.sub1 79 %22.sub0:vreg_128 = COPY %6.sub2 80 %22.sub2:vreg_128 = COPY %6.sub3 83 %21.sub2:vreg_128 = COPY %7.sub1 [all …]`
H A D	schedule-barrier.mir	`17 ; CHECK-NEXT: undef %1.sub2:vreg_128 = COPY $vgpr8 23 ; CHECK-NEXT: undef %5.sub2:vreg_128 = COPY $vgpr4 28 ; CHECK-NEXT: %9.sub2:sgpr_128 = V_READFIRSTLANE_B32 %5.sub2, implicit $exec 34 ; CHECK-NEXT: %12.sub2:sgpr_128 = V_READFIRSTLANE_B32 %1.sub2, implicit $exec 43 undef %42.sub2:vreg_128 = COPY $vgpr8 47 undef %45.sub2:vreg_128 = COPY $vgpr4 57 %33.sub2:sgpr_128 = V_READFIRSTLANE_B32 %45.sub2, implicit $exec 64 %27.sub2:sgpr_128 = V_READFIRSTLANE_B32 %42.sub2, implicit $exec`
H A D	detect-dead-lanes.mir	`12 # CHECK: S_NOP 0, implicit undef %3.sub2 34 S_NOP 0, implicit %3.sub2 50 # CHECK: S_NOP 0, implicit %1.sub2 59 # CHECK: S_NOP 0, implicit %4.sub2 95 S_NOP 0, implicit %1.sub2 104 S_NOP 0, implicit %4.sub2 140 # CHECK: S_NOP 0, implicit %9.sub2 189 S_NOP 0, implicit %9.sub2 297 …%5 = REG_SEQUENCE %4.sub0, %subreg.sub0, %4.sub2, %subreg.sub1, %4.sub1, %subreg.sub2, %4.sub3, %s… 374 # CHECK: S_NOP 0, implicit %2.sub2 [all …]`
H A D	spill-empty-live-interval.mir	`46 # CHECK: undef %1.sub2:vreg_128 = V_MOV_B32_e32 1786773504, implicit $exec 49 # CHECK-NEXT: S_NOP 0, implicit %1.sub2 50 # CHECK-NEXT: undef %2.sub2:vreg_128 = V_MOV_B32_e32 0, implicit $exec 51 # CHECK-NEXT: S_NOP 0, implicit %2.sub2 62 undef %0.sub2:vreg_128 = V_MOV_B32_e32 0, implicit $exec 63 undef %1.sub2:vreg_128 = V_MOV_B32_e32 1786773504, implicit $exec 66 S_NOP 0, implicit %1.sub2 68 S_NOP 0, implicit %0.sub2`
H A D	expand-si-indirect.mir	46 …ENCE killed %5, %subreg.sub0, killed %6, %subreg.sub1, killed %7, %subreg.sub2, killed %8, %subreg… 55 …E killed %29, %subreg.sub0, killed %28, %subreg.sub1, killed %27, %subreg.sub2, killed %26, %subre… 61 …E killed %34, %subreg.sub0, killed %33, %subreg.sub1, killed %32, %subreg.sub2, killed %31, %subre… 67 …E killed %39, %subreg.sub0, killed %38, %subreg.sub1, killed %37, %subreg.sub2, killed %36, %subre… 70 %42:vgpr_32 = COPY %23.sub2 73 …E killed %44, %subreg.sub0, killed %43, %subreg.sub1, killed %42, %subreg.sub2, killed %41, %subre… 79 …E killed %49, %subreg.sub0, killed %48, %subreg.sub1, killed %47, %subreg.sub2, killed %46, %subre… 85 …E killed %54, %subreg.sub0, killed %53, %subreg.sub1, killed %52, %subreg.sub2, killed %51, %subre… 91 …E killed %59, %subreg.sub0, killed %58, %subreg.sub1, killed %57, %subreg.sub2, killed %56, %subre… 94 %62:vgpr_32 = COPY %25.sub2 [all …]
H A D	coalescing-with-subregs-in-loop-bug.mir	5 # Inside the loop, %29.sub2 is used in a V_LSHLREV whose result is then used 14 # %39:vgpr_32 = V_LSHLREV_B32_e32 2, %29.sub2, implicit $exec 25 # in the loop, but the sub2 used in the V_LSHLREV is not modified in the loop. 27 # The bug is that the coalesced value has a L00000004 subrange (for sub2) that 29 # Rename Independent Subregs separates sub2 into its own register, and it is 34 # GCN: V_LSHLREV_B32_e32 2, [[val:%[0-9][0-9]*]].sub2 51 %28.sub2:vreg_128 = COPY killed %11 66 %39:vgpr_32 = V_LSHLREV_B32_e32 2, %29.sub2, implicit $exec 94 %32.sub2:vreg_128 = COPY %33
H A D	mubuf-legalize-operands.mir	26 # W64: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec 52 # W32: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec 85 … %6:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3 103 # W64: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec 129 # W32: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec 162 … %6:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3 180 # W64: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec 206 # W32: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec 252 # ADDR64: %18:sgpr_128 = REG_SEQUENCE %15, %subreg.sub0_sub1, %16, %subreg.sub2, %17, %subreg.sub3 294 # W64-NO-ADDR64: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec [all …]
H A D	coalescer-identical-values-undef.mir	`13 undef %0.sub2:sgpr_128 = COPY $sgpr4 19 %0.sub0:sgpr_128 = COPY %0.sub2 20 %0.sub1:sgpr_128 = COPY %0.sub2 28 $sgpr2 = COPY %0.sub2`
H A D	merge-tbuffer.mir	80 # GFX9: %{{[0-9]+}}:vgpr_32 = COPY killed %7.sub2 140 # GFX9: %{{[0-9]+}}:vgpr_32 = COPY killed %16.sub2 145 # GFX9: %{{[0-9]+}}:vgpr_32 = COPY killed %19.sub2 177 # GFX9: %{{[0-9]+}}:vgpr_32 = COPY killed %16.sub2 182 # GFX9: %{{[0-9]+}}:vgpr_32 = COPY killed %19.sub2 214 # GFX9: %{{[0-9]+}}:vgpr_32 = COPY killed %16.sub2 219 # GFX9: %{{[0-9]+}}:vgpr_32 = COPY killed %19.sub2 896 # GFX10: %{{[0-9]+}}:vgpr_32 = COPY killed %7.sub2 956 # GFX10: %{{[0-9]+}}:vgpr_32 = COPY killed %16.sub2 961 # GFX10: %{{[0-9]+}}:vgpr_32 = COPY killed %19.sub2 [all …]
H A D	undef-subreg-use-after-coalesce.mir	`4 # The copy from %0 to %1 introduces liveness for %3.sub2. After 5 # coalescing, the use of %1.sub2 needs to be marked undef. The 17 ; CHECK-NEXT: S_ENDPGM 0, implicit undef %0.sub2 21 S_ENDPGM 0, implicit %1.sub2 70 ; CHECK-NEXT: S_NOP 0, implicit undef %2.sub2 78 S_NOP 0, implicit %3.sub2`
H A D	regcoalescer-resolve-lane-conflict-by-subranges.mir	28 …; GCN-NEXT: dead %3:vgpr_32 = V_ADD_U32_e32 [[GLOBAL_LOAD_DWORDX4_]].sub2, [[GLOBAL_LOAD_DWORDX4… 47 %4:vgpr_32 = V_ADD_U32_e32 %1.sub2, %2, implicit $exec 70 …gpr_32 = V_AND_B32_e64 [[GLOBAL_LOAD_DWORDX4_]].sub0, [[GLOBAL_LOAD_DWORDX4_]].sub2, implicit $exec 74 …; GCN-NEXT: dead %3:vgpr_32 = V_ADD_U32_e32 [[GLOBAL_LOAD_DWORDX4_]].sub2, [[COPY1]], implicit $… 89 early-clobber %2:vgpr_32 = V_AND_B32_e64 %1.sub0, %1.sub2, implicit $exec 93 %4:vgpr_32 = V_ADD_U32_e32 %1.sub2, %2, implicit $exec 165 …; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_]].sub2:vreg_128 = V_AND_B32_e64 [[GLOBAL_LOAD_DWORDX4_]].sub0… 170 …gpr_32 = V_ADD_U32_e32 [[GLOBAL_LOAD_DWORDX4_]].sub1, [[GLOBAL_LOAD_DWORDX4_]].sub2, implicit $exec 186 %1.sub2:vreg_128 = V_AND_B32_e64 %2, %2, implicit $exec 191 %4:vgpr_32 = V_ADD_U32_e32 %1.sub1, %1.sub2, implicit $exec
H A D	greedy-liverange-priority.mir	`25 %27.sub2:vreg_128 = COPY %27.sub0 29 %16.sub2:sgpr_256 = COPY %16.sub0 41 %30.sub2:vreg_128 = COPY %30.sub1 69 %25.sub2:sgpr_256 = COPY %25.sub0 91 %25.sub2:sgpr_256 = COPY %25.sub0 95 %28.sub2:vreg_128 = COPY %28.sub0`
H A D	coalescing-subreg-was-undef-but-became-def.mir	`19 ; CHECK-NEXT: undef %4.sub2:sgpr_128 = S_MOV_B32 0 34 undef %1.sub2:sgpr_128 = COPY %0 36 undef %3.sub2:sgpr_128 = COPY %0 43 %4.sub2:sgpr_128 = COPY killed %0`
H A D	rename-independent-subregs-mac-operands.mir	`59 %13.sub2 = COPY killed %8 65 FLAT_STORE_DWORD undef %10, %1.sub2, 0, 0, implicit $exec, implicit $flat_scr 82 # GCN: undef %9.sub2:vreg_128 = COPY %7.sub0 89 # GCN: BUFFER_STORE_DWORD_OFFEN %9.sub2, %0, 122 %6.sub2 = COPY %6.sub0 132 %6.sub2 = COPY %6.sub0 136 … BUFFER_STORE_DWORD_OFFEN %6.sub2, %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 8, 0, 0, 0, implicit $exec`
H A D	coalescer-extend-pruned-subrange.mir	`17 %3.sub2:sgpr_128 = COPY %0 29 %13:vgpr_32 = V_OR_B32_e32 %11, %12.sub2, implicit $exec 49 %22.sub2:sgpr_128 = COPY %8 69 %25:vgpr_32 = V_AND_B32_e32 target-flags(amdgpu-gotprel32-hi) 1, %10.sub2, implicit $exec 100 %40.sub2:vreg_128 = COPY %38`
/llvm-project-15.0.7/flang/test/Semantics/
H A D	assign09.f90	`31 call sub2(float) 40 call sub2(sqrt) ! ok 49 call sub2(noInterfaceExternal) 62 subroutine sub2(p) subroutine`
H A D	resolve16.f90	`7 procedure :: sub1, sub2 12 subroutine sub2 subroutine`
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A D	sub-splat-sub.ll	`13 %sub2 = sub <16 x i8> zeroinitializer, %sh_prom 14 ret <16 x i8> %sub2 26 %sub2 = sub <vscale x 16 x i8> zeroinitializer, %sh_prom 27 ret <vscale x 16 x i8> %sub2`
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	llvm.amdgcn.s.buffer.load.ll	2704 ; GFX6-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub2 2750 ; GFX7-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub2 2796 ; GFX8-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub2 2846 ; GFX6-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub2 2890 ; GFX7-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub2 2934 ; GFX8-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub2 2989 ; GFX6-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub2 3037 ; GFX7-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub2 3085 ; GFX8-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub2 3136 ; GFX6-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub2 [all …]
H A D	llvm.amdgcn.raw.tbuffer.store.f16.ll	15 …ENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg… 29 …ENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg… 48 …ENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg… 66 …ENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg… 114 …ENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg… 145 ; UNPACKED-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub2 195 ; PACKED-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub2 251 ; UNPACKED-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub2 304 ; PACKED-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub2 364 ; UNPACKED-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub2 [all …]
H A D	llvm.amdgcn.raw.buffer.store.format.f16.ll	14 …UENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg… 28 …UENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg… 47 …UENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg… 60 …UENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg… 78 …UENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg… 96 …UENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg… 136 …UENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg… 177 ; UNPACKED-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub2 229 ; PACKED-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub2 490 ; UNPACKED-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub2 [all …]
H A D	llvm.amdgcn.raw.buffer.atomic.fadd.ll	16 …ENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg… 30 …ENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg… 49 …ENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg… 63 …ENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg… 83 …ENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg… 96 …ENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg… 115 …ENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg… 160 ; GFX908-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub2 215 ; GFX90A-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub2 274 ; GFX908-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub2 [all …]
H A D	llvm.amdgcn.raw.buffer.store.format.f32.ll	14 …UENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg… 33 …UENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg… 51 …UENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg… 72 …UENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg… 76 …]]:vreg_96 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2 94 …UENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg… 99 …ENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg… 118 …UENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg… 133 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub2 176 …UENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg… [all …]
/llvm-project-15.0.7/flang/test/Lower/
H A D	call-implicit.f90	`8 call sub2(i) 13 call sub2("01234")`

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TaskScheduler
dpdk
expo
f-stack
freebsd-12.1
freebsd-13.1
freebsd-14.2
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libevent-2.1.12
libpciaccess
libtiff-4.0.7
lighttpd1.4
linux-6.15
llvm-project-15.0.7
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memcached-1.4.29
memcached-1.6.32
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