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Searched refs:stm (Results 1 – 25 of 74) sorted by relevance

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/llvm-project-15.0.7/llvm/test/tools/llvm-mca/ARM/
H A Dmemcpy-ldm-stm.s5 stm r0!, {r3, r4, r5, r6, r12, lr}
27 # CHECK-NEXT: 5 1 2.00 * stm r0!, {r3, r4, r5, r6, r12, lr}
44 # CHECK-NEXT: - - - 2.00 1.37 1.63 stm r0!, {r3, r4, r5, r6, r12, lr}
51 # CHECK-NEXT: [0,1] .D=================eER . . stm r0!, {r3, r4, r5, r6, r12, lr}
53 # CHECK-NEXT: [1,1] . D=================eER. . stm r0!, {r3, r4, r5, r6, r12, lr}
55 # CHECK-NEXT: [2,1] . . D==================eER stm r0!, {r3, r4, r5, r6, r12, lr}
65 # CHECK-NEXT: 1. 3 18.3 0.3 0.0 stm r0!, {r3, r4, r5, r6, r12, lr}
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Darm-load-store-multiple-deprecated.s15 .global stm
16 .type stm,%function
17 stm: label
18 stm sp!, {r0, pc}
21 @ CHECK: stm sp!, {r0, pc}
23 stm r1!, {r0, sp, pc}
27 stm r2!, {sp, pc}
31 stm sp!, {pc}
33 @ CHECK: stm sp!, {pc}
164 stm r0!, {r0, sp}
[all …]
H A Dthumb-load-store-multiple.s43 .global stm
44 .type stm,%function
45 stm: label
46 stm r0!, {r1, sp}
48 stm r0!, {r2, pc}
50 stm r0!, {sp, pc}
H A Dthumb-diagnostics.s149 stm r1, {r2, r6}
150 stm r1!, {r2, r9}
151 stm r2!, {r2, r9}
153 stm r1!, {r2, sp}
158 @ CHECK-ERRORS: stm r1, {r2, r6}
163 @ CHECK-ERRORS: stm r1!, {r2, r9}
166 @ CHECK-ERRORS-V8: stm r2!, {r2, r9}
172 @ CHECK-ERRORS-V7M: stm r1!, {r2, sp}
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb/
H A Dldm-stm-base-materialization.ll17 ; CHECK-NEXT: stm r[[NSB]]!, {r[[R1]], r[[R2]], r[[R3]]}
19 ; CHECK-NEXT: stm r[[NSB]]!, {r[[R1]], r[[R2]], r[[R3]]}
38 ; CHECK-NEXT: stm r[[NSB]]!, {r[[R1]], r[[R2]], r[[R3]]}
40 ; CHECK-NEXT: stm r[[NSB]]!, {r[[R1]], r[[R2]], r[[R3]], r[[R4]]}
59 ; CHECK-NEXT: stm r[[NSB]]!, {r[[R1]], r[[R2]], r[[R3]], r[[R4]]}
61 ; CHECK-NEXT: stm r[[NSB]]!, {r[[R1]], r[[R2]], r[[R3]], r[[R4]]}
80 ; CHECK-NEXT: stm r[[NSB]]!, {r[[R1]], r[[R2]], r[[R3]]}
82 ; CHECK-NEXT: stm r[[NSB]]!, {r[[R1]], r[[R2]], r[[R3]]}
84 ; CHECK-NEXT: stm r[[NSB]]!, {r[[R1]], r[[R2]], r[[R3]]}
H A Dstm-deprecated.ll19 ; CHECK-NOT: stm
32 ; CHECK-T2: stm.w r2, {r0, r1, r2}
33 ; CHECK-NOT: stm r2!, {r0, r1, r2}
50 ; CHECK-T2: stm.w r2, {r0, r1, r2}
51 ; CHECK-NOT: stm r2!, {r0, r1, r2}
65 ; FIXME: We should be using stm in both thumb1 and thumb2
70 ; CHECK-T2: stm r0!, {r0, r1, r2}
H A Dldm-stm-base-materialization-thumb2.ll18 ; CHECK-NEXT: stm{{(\.w)?}} [[SB]], {[[R1]], [[R2]], [[R3]], [[R4]], [[R5]], [[R6]]}
37 ; CHECK-NEXT: stm{{(\.w)?}} [[SB]]!, {[[R1]], [[R2]], [[R3]]}
39 ; CHECK-NEXT: stm{{(\.w)?}} [[SB]], {[[R1]], [[R2]], [[R3]], [[R4]]}
58 ; CHECK-NEXT: stm{{(\.w)?}} [[SB]]!, {[[R1]], [[R2]], [[R3]], [[R4]]}
60 ; CHECK-NEXT: stm{{(\.w)?}} [[SB]], {[[R1]], [[R2]], [[R3]], [[R4]]}
79 ; CHECK-NEXT: stm{{(\.w)?}} [[SB]]!, {[[R1]], [[R2]], [[R3]], [[R4]]}
81 ; CHECK-NEXT: stm{{(\.w)?}} [[SB]], {[[R1]], [[R2]], [[R3]], [[R4]], [[R5]]}
H A Duxth.ll48 ; V6M-NEXT: stm r0!, {r2}
78 ; V6M-NEXT: stm r0!, {r4}
106 ; V6M-NEXT: stm r0!, {r2}
136 ; V6M-NEXT: stm r0!, {r4}
H A Dldm-stm-postinc.ll46 ; CHECK: stm {{r[0-9]}}!, {r{{[0-9]}}}
65 ; CHECK-NOT: stm
83 ; Make sure we don't transform str->stm when unaligned loads are allowed.
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dldm-stm-base-materialization.ll18 ; CHECK-NEXT: stm [[NSB]], {[[R1]], [[R2]], [[R3]], [[R4]], [[R5]], [[R6]]}
37 ; CHECK-NEXT: stm [[NSB]]!, {[[R1]], [[R2]], [[R3]]}
39 ; CHECK-NEXT: stm [[NSB]], {[[R1]], [[R2]], [[R3]], [[R4]]}
58 ; CHECK-NEXT: stm [[NSB]]!, {[[R1]], [[R2]], [[R3]], [[R4]]}
60 ; CHECK-NEXT: stm [[NSB]], {[[R1]], [[R2]], [[R3]], [[R4]]}
79 ; CHECK-NEXT: stm [[NSB]]!, {[[R1]], [[R2]], [[R3]], [[R4]]}
81 ; CHECK-NEXT: stm [[NSB]], {[[R1]], [[R2]], [[R3]], [[R4]], [[R5]]}
H A Dmemcpy-ldm-stm.ll23 ; CHECK-NEXT: stm{{(\.w)?}} [[SB]]!,
38 ; CHECKV6-NEXT: stm{{(\.w)?}} [[SB]]!,
76 ; 3 ldm/stm pairs in v6; 2 in v7
78 ; CHECK: stm{{(\.w)?}} {{[rl0-9]+!?}}, [[REGLIST1]]
80 ; CHECK: stm{{(\.w)?}} {{[rl0-9]+!?}}, [[REGLIST2]]
82 ; CHECKV6: stm {{r[0-7]!?}}, [[REGLIST3]]
84 ; CHECKV7-NOT: stm
H A Dldm-stm-i256.ll5 ; being used as a test of optimizations related to ldm/stm.
32 ; CHECK-DAG: stm r0
36 ; CHECK-DAG: stm r1
H A Dwrong-t2stmia-size-opt.ll21 ; Check that stm writes three registers. The bug caused one of registers (LR,
24 ; CHECK: stm{{[^,]*}}, {{{.*,.*,.*}}}
H A D2014-02-21-byval-reg-split-alignment.ll20 ; CHECK: stm [[SCRATCH]], {r1, r2, r3}
55 ; CHECK: stm [[SCRATCH]], {r0, r1, r2}
92 ; CHECK: stm [[SCRATCH]], {r0, r1, r2, r3}
H A Dload-store-flags.ll9 ; CHECK: stm [[NEWBASE]]!, {r0, r1, r2}
30 ; CHECK: stm [[NEWBASE]]!, {r0, r1, r2}
H A Darm-modifier.ll49 ; CHECK: stm {{lr|r[0-9]+}}, {[[REG1:(r[0-9]+)]], r{{[0-9]+}}}
54 %0 = call i64 asm sideeffect "stm ${0:m}, ${1:M}\0A\09adds $3, $1\0A\09", "=*m,=r,1,r"(i64** elemen…
H A Dnaked-no-prolog.ll6 ; CHECK-NOT: stm
H A Dgpr-paired-spill.ll28 ; CHECK-WITHOUT-LDRD-DAG: stm [[ADDRREG]], {r{{[0-9]+}}, r{{[0-9]+}}}
29 ; CHECK-WITHOUT-LDRD-DAG: stm sp, {r{{[0-9]+}}, r{{[0-9]+}}}
H A D2013-05-13-AAPCS-byval-padding2.ll13 ;CHECK: stm r12, {r0, r1, r2, r3}
H A D2013-05-13-AAPCS-byval-padding.ll20 ;CHECK: stm r0, {r1, r2, r3}
H A Dstm.ll12 ; CHECK: stm
H A D2012-10-18-PR14099-ByvalFrameAddress.ll17 ; CHECK: stm r0, {r1, r2, r3}
H A Dbig-endian-vector-callee.ll1059 ; SOFT-NEXT: stm sp, {r0, r1, r2, r3}
1075 ; HARD-NEXT: stm sp, {r0, r1, r2, r3}
1098 ; SOFT-NEXT: stm sp, {r0, r1, r2, r3}
1113 ; HARD-NEXT: stm sp, {r0, r1, r2, r3}
1136 ; SOFT-NEXT: stm sp, {r0, r1, r2, r3}
1151 ; HARD-NEXT: stm sp, {r0, r1, r2, r3}
1174 ; SOFT-NEXT: stm sp, {r0, r1, r2, r3}
1189 ; HARD-NEXT: stm sp, {r0, r1, r2, r3}
1213 ; SOFT-NEXT: stm sp, {r0, r1, r2, r3}
1229 ; HARD-NEXT: stm sp, {r0, r1, r2, r3}
[all …]
H A Dvarargs-spill-stack-align-nacl.ll31 ; CHECK-NEXT: stm r0, {r1, r2, r3}
/llvm-project-15.0.7/libunwind/src/
H A DUnwindRegistersSave.S795 stm r0!, {r0-r7}
799 stm r0!, {r1-r3}
813 @ 32bit thumb-2 restrictions for stm:
816 stm r0, {r0-r12}

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