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/llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Exynos/
H A Dasimd-st3.s6 st3 {v0.s, v1.s, v2.s}[0], [sp] label
7 st3 {v0.2s, v1.2s, v2.2s}, [sp] label
9 st3 {v0.d, v1.d, v2.d}[0], [sp] label
10 st3 {v0.2d, v1.2d, v2.2d}, [sp] label
12 st3 {v0.s, v1.s, v2.s}[0], [sp], #12 label
13 st3 {v0.2s, v1.2s, v2.2s}, [sp], #24 label
15 st3 {v0.d, v1.d, v2.d}[0], [sp], #24 label
18 st3 {v0.s, v1.s, v2.s}[0], [sp], x0 label
19 st3 {v0.2s, v1.2s, v2.2s}, [sp], x0 label
21 st3 {v0.d, v1.d, v2.d}[0], [sp], x0 label
[all …]
/llvm-project-15.0.7/clang/test/SemaCXX/
H A Dcxx2b-p2266-disable-with-msvc-compat.cpp114 nocopy st3(nocopy x) { return x; } in st3() function
119 nocopy st3(nocopy x) { return x; } in st3() function
125 nocopy st3(nocopy x) { return x; } in st3() function
129 nocopy st3(nocopy x) { return x; } in st3() function
137 nocopy st3(nocopy x) { return x; } in st3() function
142 nocopy st3(nocopy x) { return x; } in st3() function
148 nocopy st3(nocopy x) { return x; } in st3() function
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Darm64-simd-ldst.s239 st3.8b {v4, v5, v6}, [x19]
240 st3.16b {v4, v5, v6}, [x19]
241 st3.4h {v4, v5, v6}, [x19]
242 st3.8h {v4, v5, v6}, [x19]
243 st3.2s {v4, v5, v6}, [x19]
244 st3.4s {v4, v5, v6}, [x19]
245 st3.2d {v4, v5, v6}, [x19]
250 st3.8h {v30, v31, v0}, [x9]
251 st3.2s {v2, v3, v4}, [x19]
252 st3.4s {v7, v8, v9}, [x29]
[all …]
H A Dneon-simd-ldst-multi-elem.s174 st3 { v31.4s, v0.4s, v1.4s }, [sp]
175 st3 { v0.2d, v1.2d, v2.2d }, [x0]
176 st3 { v0.8b, v1.8b, v2.8b }, [x0]
178 st3 { v31.2s, v0.2s, v1.2s }, [sp]
187 st3 { v0.16b-v2.16b }, [x0]
188 st3 { v15.8h-v17.8h }, [x15]
189 st3 { v31.4s-v1.4s }, [sp]
190 st3 { v0.2d-v2.2d }, [x0]
191 st3 { v0.8b-v2.8b }, [x0]
192 st3 { v15.4h-v17.4h }, [x15]
[all …]
H A Dneon-simd-ldst-one-elem.s148 st3 { v0.b, v1.b, v2.b }[9], [x0]
149 st3 { v15.h, v16.h, v17.h }[7], [x15]
150 st3 { v31.s, v0.s, v1.s }[3], [sp]
151 st3 { v0.d, v1.d, v2.d }[1], [x0]
309 st3 { v0.b, v1.b, v2.b }[9], [x0], #3
310 st3 { v15.h, v16.h, v17.h }[7], [x15], #6
311 st3 { v31.s, v0.s, v1.s }[3], [sp], x3
312 st3 { v0.d, v1.d, v2.d }[1], [x0], x6
H A Dneon-simd-post-ldst-multi-elem.s343 st3 { v0.16b, v1.16b, v2.16b }, [x0], x1
344 st3 { v15.8h, v16.8h, v17.8h }, [x15], x2
345 st3 { v31.4s, v0.4s, v1.4s }, [sp], #48
346 st3 { v0.2d, v1.2d, v2.2d }, [x0], #48
347 st3 { v0.8b, v1.8b, v2.8b }, [x0], x2
348 st3 { v15.4h, v16.4h, v17.4h }, [x15], x3
349 st3 { v31.2s, v0.2s, v1.2s }, [sp], #24
/llvm-project-15.0.7/clang/test/CodeGen/
H A Daapcs-bitfield.c488 struct st3 { struct
564 int st3_check_load(struct st3 *m) { in st3_check_load()
640 void st3_check_store(struct st3 *m) { in st3_check_store()
H A Dstruct-x86-darwin.c15 struct STest3 {char a; short b; int c; } st3; variable
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-intrinsics-stN-reg-reg-addr-mode.ll139 call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
160 call void @llvm.aarch64.sve.st3.nxv8i16(<vscale x 8 x i16> %v0,
177 call void @llvm.aarch64.sve.st3.nxv8f16(<vscale x 8 x half> %v0,
198 call void @llvm.aarch64.sve.st3.nxv4i32(<vscale x 4 x i32> %v0,
215 call void @llvm.aarch64.sve.st3.nxv4f32(<vscale x 4 x float> %v0,
236 call void @llvm.aarch64.sve.st3.nxv2i64(<vscale x 2 x i64> %v0,
253 call void @llvm.aarch64.sve.st3.nxv2f64(<vscale x 2 x double> %v0,
418 declare void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i…
419 declare void @llvm.aarch64.sve.st3.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1…
420 declare void @llvm.aarch64.sve.st3.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i3…
[all …]
H A Darm64-st1.ll538 ; CHECK: st3.b
545 ; CHECK: st3.h
552 ; CHECK: st3.s
559 ; CHECK: st3.d
616 ; CHECK: st3.8b
656 ; CHECK: st3.16b
696 ; CHECK: st3.4h
736 ; CHECK: st3.8h
776 ; CHECK: st3.2s
816 ; CHECK: st3.4s
[all …]
H A Darm64-copy-tuple.ll91 …tail call void @llvm.aarch64.neon.st3.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, i8…
94 …tail call void @llvm.aarch64.neon.st3.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, i8…
110 …tail call void @llvm.aarch64.neon.st3.v16i8.p0i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2…
113 …tail call void @llvm.aarch64.neon.st3.v16i8.p0i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2…
144 declare void @llvm.aarch64.neon.st3.v8i8.p0i8(<8 x i8>, <8 x i8>, <8 x i8>, i8*)
145 declare void @llvm.aarch64.neon.st3.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, i8*)
H A Dsve-intrinsics-stores.ll159 call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
179 call void @llvm.aarch64.sve.st3.nxv8i16(<vscale x 8 x i16> %v0,
195 call void @llvm.aarch64.sve.st3.nxv8f16(<vscale x 8 x half> %v0,
211 call void @llvm.aarch64.sve.st3.nxv8bf16(<vscale x 8 x bfloat> %v0,
231 call void @llvm.aarch64.sve.st3.nxv4i32(<vscale x 4 x i32> %v0,
247 call void @llvm.aarch64.sve.st3.nxv4f32(<vscale x 4 x float> %v0,
267 call void @llvm.aarch64.sve.st3.nxv2i64(<vscale x 2 x i64> %v0,
283 call void @llvm.aarch64.sve.st3.nxv2f64(<vscale x 2 x double> %v0,
299 call void @llvm.aarch64.sve.st3.nxv2p0i8(<vscale x 2 x i8*> %v0,
680 declare void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i…
[all …]
H A Dsve-intrinsics-stN-reg-imm-addr-mode.ll223 call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
241 call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
259 call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
277 call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
295 call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
312 call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
329 call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
350 call void @llvm.aarch64.sve.st3.nxv8i16(<vscale x 8 x i16> %v0,
367 call void @llvm.aarch64.sve.st3.nxv8f16(<vscale x 8 x half> %v0,
388 call void @llvm.aarch64.sve.st3.nxv4i32(<vscale x 4 x i32> %v0,
[all …]
H A Dmulti-vector-store-size.ll4 declare void @llvm.aarch64.neon.st3.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, float*)
30 …tail call void @llvm.aarch64.neon.st3.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %c…
H A Dfp16-vector-load-store.ll184 declare void @llvm.aarch64.neon.st3.v4f16.p0v4f16(<4 x half>, <4 x half>, <4 x half>, <4 x half>*)
190 declare void @llvm.aarch64.neon.st3.v8f16.p0v8f16(<8 x half>, <8 x half>, <8 x half>, <8 x half>*)
232 ; CHECK: st3 { v0.4h, v1.4h, v2.4h }, [x0]
234 …tail call void @llvm.aarch64.neon.st3.v4f16.p0v4f16(<4 x half> %b, <4 x half> %c, <4 x half> %d, <…
286 ; CHECK: st3 { v0.8h, v1.8h, v2.8h }, [x0]
288 …tail call void @llvm.aarch64.neon.st3.v8f16.p0v8f16(<8 x half> %b, <8 x half> %c, <8 x half> %d, <…
417 ; CHECK: st3 { v0.h, v1.h, v2.h }[2], [x0]
471 ; CHECK: st3 { v0.h, v1.h, v2.h }[2], [x0]
H A Darm64-indexed-vector-ldst.ll5404 ; CHECK-NEXT: st3.16b { v0, v1, v2 }, [x0], x2
5420 ; CHECK-NEXT: st3.8b { v0, v1, v2 }, [x0], #24
5433 ; CHECK-NEXT: st3.8b { v0, v1, v2 }, [x0], x2
5463 ; CHECK-NEXT: st3.8h { v0, v1, v2 }, [x0], x8
5493 ; CHECK-NEXT: st3.4h { v0, v1, v2 }, [x0], x8
5523 ; CHECK-NEXT: st3.4s { v0, v1, v2 }, [x0], x8
5553 ; CHECK-NEXT: st3.2s { v0, v1, v2 }, [x0], x8
5583 ; CHECK-NEXT: st3.2d { v0, v1, v2 }, [x0], x8
5643 ; CHECK-NEXT: st3.4s { v0, v1, v2 }, [x0], x8
5673 ; CHECK-NEXT: st3.2s { v0, v1, v2 }, [x0], x8
[all …]
/llvm-project-15.0.7/lldb/test/Shell/Register/
H A Dx86-64-fp-write.test24 register write st3 "{0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x80}"
43 # CHECK-DAG: st3 = { 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x80 }
H A Dx86-fp-write.test23 register write st3 "{0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x80}"
45 # CHECK-DAG: st3 = { 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x80 }
/llvm-project-15.0.7/compiler-rt/lib/sanitizer_common/tests/
H A Dsanitizer_libc_test.cpp146 struct stat st1, st2, st3; in TEST() local
149 EXPECT_EQ(0u, internal_fstat(fd, &st3)); in TEST()
150 EXPECT_EQ(fsize, (uptr)st3.st_size); in TEST()
/llvm-project-15.0.7/clang/test/CodeGen/X86/
H A Dx86_32-arguments-iamcu.c38 void smallStructs(st4_t st1, st4_t st2, st4_t st3) {} in smallStructs() argument
/llvm-project-15.0.7/llvm/test/Transforms/EarlyCSE/AArch64/
H A Dintrinsics.ll173 ; Check that @llvm.aarch64.neon.st3 is not optimized away by Early CSE due to
174 ; mismatch between st2 and st3.
176 ; CHECK: call void @llvm.aarch64.neon.st3.v4i32.p0
193 call void @llvm.aarch64.neon.st3.v4i32.p0(<4 x i32> %3, <4 x i32> %2, <4 x i32> %2, ptr %a)
210 declare void @llvm.aarch64.neon.st3.v4i32.p0(<4 x i32>, <4 x i32>, <4 x i32>, ptr nocapture)
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AArch64/
H A Darm64-advsimd.txt1117 # CHECK: st3.8b { v1, v2, v3 }, [x1]
1118 # CHECK: st3.16b { v5, v6, v7 }, [x2]
1119 # CHECK: st3.2s { v10, v11, v12 }, [x0]
1191 # CHECK: st3.8b { v1, v2, v3 }, [x2], x3
1192 # CHECK: st3.16b { v2, v3, v4 }, [x2], x4
1193 # CHECK: st3.4h { v4, v5, v6 }, [x3], x5
1194 # CHECK: st3.8h { v7, v8, v9 }, [x4], x6
1240 # CHECK: st3.b { v1, v2, v3 }[2], [x3]
1241 # CHECK: st3.d { v2, v3, v4 }[1], [x4]
1242 # CHECK: st3.h { v3, v4, v5 }[2], [x6]
[all …]
/llvm-project-15.0.7/clang/test/CodeGen/arc/
H A Darguments.c126 void st3(s16 a, s16 b, s16 c) {} in st3() function
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dipra-reg-usage.ll6 …4 $k5 $k6 $k7 $mm0 $mm1 $mm2 $mm3 $mm4 $mm5 $mm6 $mm7 $r11 $st0 $st1 $st2 $st3 $st4 $st5 $st6 $st7…
/llvm-project-15.0.7/lldb/test/Shell/Register/Core/Inputs/
H A Dx86-fp.check10 # CHECK-DAG: st3 = {0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x80}

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