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/llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Exynos/
H A Dasimd-st2.s6 st2 {v0.s, v1.s}[0], [sp] label
7 st2 {v0.2s, v1.2s}, [sp] label
9 st2 {v0.d, v1.d}[0], [sp] label
10 st2 {v0.2d, v1.2d}, [sp] label
12 st2 {v0.s, v1.s}[0], [sp], #8 label
13 st2 {v0.2s, v1.2s}, [sp], #16 label
16 st2 {v0.2d, v1.2d}, [sp], #32 label
18 st2 {v0.s, v1.s}[0], [sp], x0 label
19 st2 {v0.2s, v1.2s}, [sp], x0 label
21 st2 {v0.d, v1.d}[0], [sp], x0 label
[all …]
/llvm-project-15.0.7/clang/test/OpenMP/
H A Dtarget_map_codegen_31.cpp79 struct ST st2; in explicit_maps_single() local
163 : a, st1.j, st2.i) map(tofrom \ in explicit_maps_single()
164 : st2.j) in explicit_maps_single()
170 st2.i++; in explicit_maps_single()
171 st2.j++; in explicit_maps_single()
H A Dtarget_map_codegen_hold.cpp778 struct ST st2; in explicit_maps_single() local
783 map(ompx_hold, tofrom : a, st1.j, st2.i) \ in explicit_maps_single()
784 map(tofrom : st2.j) in explicit_maps_single()
790 st2.i++; in explicit_maps_single()
791 st2.j++; in explicit_maps_single()
/llvm-project-15.0.7/clang/test/SemaCXX/
H A Dcxx2b-p2266-disable-with-msvc-compat.cpp113 int &st2(int &&x) { return x; } // cxx2b-error {{cannot bind to a temporary}} in st2() function
118 int &st2(int &&x) { return x; } // cxx2b-error {{cannot bind to a temporary}} in st2() function
124 int &st2(int &&x) { return x; } // cxx2b-error {{cannot bind to a temporary}} in st2() function
128 int &st2(int &&x) { return x; } // cxx2b-error {{cannot bind to a temporary}} in st2() function
136 int &st2(int &&x) { return x; } // new-error {{cannot bind to a temporary}} in st2() function
141 int &st2(int &&x) { return x; } // new-error {{cannot bind to a temporary}} in st2() function
147 int &st2(int &&x) { return x; } // new-error {{cannot bind to a temporary}} in st2() function
/llvm-project-15.0.7/llvm/test/CodeGen/XCore/
H A DbyVal.ll52 %struct.st2 = type { i32 }
53 declare void @f2(i32, %struct.st2*) nounwind
54 define void @f2Test(%struct.st2* byval(%struct.st2) %s2, i32 %i, ...) nounwind {
56 call void @f2(i32 %i, %struct.st2* %s2)
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Dneon-simd-ldst-multi-elem.s139 st2 { v0.16b, v1.16b }, [x0]
141 st2 { v31.4s, v0.4s }, [sp]
142 st2 { v0.2d, v1.2d }, [x0]
143 st2 { v0.8b, v1.8b }, [x0]
145 st2 { v31.2s, v0.2s }, [sp]
154 st2 { v0.16b-v1.16b }, [x0]
155 st2 { v15.8h-v16.8h }, [x15]
156 st2 { v31.4s-v0.4s }, [sp]
157 st2 { v0.2d-v1.2d }, [x0]
158 st2 { v0.8b-v1.8b }, [x0]
[all …]
H A Darm64-simd-ldst.s195 st2.8b {v4, v5}, [x19]
196 st2.16b {v4, v5}, [x19]
197 st2.4h {v4, v5}, [x19]
198 st2.8h {v4, v5}, [x19]
199 st2.2s {v4, v5}, [x19]
200 st2.4s {v4, v5}, [x19]
201 st2.2d {v4, v5}, [x19]
1212 st2.b {v4, v5}[13], [x3]
1213 st2.h {v4, v5}[2], [x3]
1214 st2.s {v4, v5}[2], [x3]
[all …]
H A Dneon-simd-ldst-one-elem.s139 st2 { v0.b, v1.b }[9], [x0]
140 st2 { v15.h, v16.h }[7], [x15]
141 st2 { v31.s, v0.s }[3], [sp]
142 st2 { v0.d, v1.d }[1], [x0]
300 st2 { v0.b, v1.b }[9], [x0], x3
301 st2 { v15.h, v16.h }[7], [x15], #4
302 st2 { v31.s, v0.s }[3], [sp], #8
303 st2 { v0.d, v1.d }[1], [x0], x0
H A Dneon-simd-post-ldst-multi-elem.s317 st2 { v0.16b, v1.16b }, [x0], x1
318 st2 { v15.8h, v16.8h }, [x15], x2
319 st2 { v31.4s, v0.4s }, [sp], #32
320 st2 { v0.2d, v1.2d }, [x0], #32
321 st2 { v0.8b, v1.8b }, [x0], x2
322 st2 { v15.4h, v16.4h }, [x15], x3
323 st2 { v31.2s, v0.2s }, [sp], #16
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dselect-st2.mir25 …G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<8 x s8>), %src2(<8 x s8>), %p…
50 …G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<16 x s8>), %src2(<16 x s8>), …
75 …G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<4 x s16>), %src2(<4 x s16>), …
100 …G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<8 x s16>), %src2(<8 x s16>), …
124 …G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<2 x s32>), %src2(<2 x s32>), …
148 …G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<4 x s32>), %src2(<4 x s32>), …
172 …G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<2 x s64>), %src2(<2 x s64>), …
196 …G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<2 x p0>), %src2(<2 x p0>), %p…
220 …G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(s64), %src2(s64), %ptr(p0) :: …
244 …G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(p0), %src2(p0), %ptr(p0) :: (s…
/llvm-project-15.0.7/llvm/test/Transforms/EarlyCSE/AArch64/
H A Dintrinsics.ll26 call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> %2, <4 x i32> %3, ptr %a)
40 ; Check that the first @llvm.aarch64.neon.st2 is optimized away by Early CSE.
59 call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> %2, <4 x i32> %2, ptr %a)
60 call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> %2, <4 x i32> %3, ptr %a)
125 call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> %2, <4 x i32> %3, ptr %a)
141 ; to mismatch between st2 and ld3.
159 call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> %2, <4 x i32> %3, ptr %a)
174 ; mismatch between st2 and st3.
177 ; CHECK: call void @llvm.aarch64.neon.st2.v4i32.p0
194 call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> %2, <4 x i32> %2, ptr %a)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64_32-neon.ll49 declare void @llvm.aarch64.neon.st2.v2f64.p0i8(%vec, %vec, i8*)
52 ; CHECK: st2.2d { v0, v1 }, [x0]
53 call void @llvm.aarch64.neon.st2.v2f64.p0i8(%vec %in1, %vec %in2, i8* %addr)
60 ; CHECK: st2.d { v0, v1 }[1], [x0]
97 ; CHECK: st2.2d { v0, v1 }, [x0], [[OFFSET]]
99 call void @llvm.aarch64.neon.st2.v2f64.p0i8(%vec %in1, %vec %in2, i8* %addr)
109 ; CHECK: st2.d { v0, v1 }[0], [x0], [[OFFSET]]
H A Darm64-copy-tuple.ll20 tail call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
23 tail call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
37 tail call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
40 tail call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
54 tail call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
57 tail call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
71 tail call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
74 tail call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
143 declare void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8>, <8 x i8>, i8*)
H A Dsched-past-vector-ldst.ll34 …tail call void @llvm.aarch64.neon.st2.v4f32.p0i8(<4 x float> %av2, <4 x float> %av1, i8* %struct_p…
46 …tail call void @llvm.aarch64.neon.st2.v4f32.p0i8(<4 x float> %av4, <4 x float> %av3, i8* %struct_p…
54 declare void @llvm.aarch64.neon.st2.v4f32.p0i8(<4 x float>, <4 x float>, i8* nocapture) #1
H A Dsve-intrinsics-stN-reg-reg-addr-mode.ll17 call void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8> %v0,
36 call void @llvm.aarch64.sve.st2.nxv8i16(<vscale x 8 x i16> %v0,
51 call void @llvm.aarch64.sve.st2.nxv8f16(<vscale x 8 x half> %v0,
70 call void @llvm.aarch64.sve.st2.nxv4i32(<vscale x 4 x i32> %v0,
85 call void @llvm.aarch64.sve.st2.nxv4f32(<vscale x 4 x float> %v0,
104 call void @llvm.aarch64.sve.st2.nxv2i64(<vscale x 2 x i64> %v0,
119 call void @llvm.aarch64.sve.st2.nxv2f64(<vscale x 2 x double> %v0,
410 declare void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i…
411 declare void @llvm.aarch64.sve.st2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1…
412 declare void @llvm.aarch64.sve.st2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1…
[all …]
H A Darm64-st1.ll505 ; CHECK: st2.b
512 ; CHECK: st2.h
519 ; CHECK: st2.s
526 ; CHECK: st2.d
605 ; CHECK: st2.8b
645 ; CHECK: st2.16b
685 ; CHECK: st2.4h
725 ; CHECK: st2.8h
765 ; CHECK: st2.2s
805 ; CHECK: st2.4s
[all …]
H A Dsve-intrinsics-stores.ll16 call void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8> %v0,
34 call void @llvm.aarch64.sve.st2.nxv8i16(<vscale x 8 x i16> %v0,
48 call void @llvm.aarch64.sve.st2.nxv8f16(<vscale x 8 x half> %v0,
62 call void @llvm.aarch64.sve.st2.nxv8bf16(<vscale x 8 x bfloat> %v0,
80 call void @llvm.aarch64.sve.st2.nxv4i32(<vscale x 4 x i32> %v0,
94 call void @llvm.aarch64.sve.st2.nxv4f32(<vscale x 4 x float> %v0,
112 call void @llvm.aarch64.sve.st2.nxv2i64(<vscale x 2 x i64> %v0,
126 call void @llvm.aarch64.sve.st2.nxv2f64(<vscale x 2 x double> %v0,
140 call void @llvm.aarch64.sve.st2.nxv2p0i8(<vscale x 2 x i8*> %v0,
670 declare void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i…
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/BasicAA/
H A Dstruct-geps.ll151 %st2 = getelementptr inbounds %struct, %struct* %st, i32 10
152 %x2 = getelementptr inbounds %struct, %struct* %st2, i64 %i, i32 0
153 %y2 = getelementptr inbounds %struct, %struct* %st2, i64 %j, i32 1
154 %z2 = getelementptr inbounds %struct, %struct* %st2, i64 %k, i32 2
183 %st2 = getelementptr inbounds %struct, %struct* %st, i32 10
184 %x2 = getelementptr inbounds %struct, %struct* %st2, i64 %i2, i32 0
185 %y2 = getelementptr inbounds %struct, %struct* %st2, i64 %j2, i32 1
186 %z2 = getelementptr inbounds %struct, %struct* %st2, i64 %k2, i32 2
/llvm-project-15.0.7/clang/test/CodeGen/
H A Daapcs-bitfield.c327 struct st2 { struct
408 int st2_check_load(struct st2 *m) { in st2_check_load()
484 void st2_check_store(struct st2 *m) { in st2_check_store()
H A Dstruct-x86-darwin.c14 struct STest2 {short a,b; int c,d; } st2; variable
/llvm-project-15.0.7/mlir/test/Integration/Dialect/SparseTensor/CPU/
H A Dsparse_out_reduction.mlir60 %st2 = sparse_tensor.convert %t2
64 %0 = call @redsum(%st1, %st2)
85 bufferization.dealloc_tensor %st2 : tensor<?x?x?xi32, #SparseTensor>
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dmultiple-uses-load-bitcast-select.ll4 define void @PR35618(i64* %st1, double* %st2) {
26 %bc = bitcast double* %st2 to i64*
/llvm-project-15.0.7/clang/test/Modules/
H A Dstddef.c13 size_t st2; variable
/llvm-project-15.0.7/lldb/test/Shell/Register/
H A Dx86-64-fp-write.test23 register write st2 "{0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}"
42 # CHECK-DAG: st2 = { 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 }
H A Dx86-fp-write.test22 register write st2 "{0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}"
44 # CHECK-DAG: st2 = { 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 }

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