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/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/X86/
H A Dx86-sse2-inseltpoison.ll12 %3 = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %2)
23 %3 = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %2)
529 declare i32 @llvm.x86.sse2.comieq.sd(<2 x double>, <2 x double>)
530 declare i32 @llvm.x86.sse2.comige.sd(<2 x double>, <2 x double>)
531 declare i32 @llvm.x86.sse2.comigt.sd(<2 x double>, <2 x double>)
532 declare i32 @llvm.x86.sse2.comile.sd(<2 x double>, <2 x double>)
533 declare i32 @llvm.x86.sse2.comilt.sd(<2 x double>, <2 x double>)
534 declare i32 @llvm.x86.sse2.comineq.sd(<2 x double>, <2 x double>)
536 declare i32 @llvm.x86.sse2.ucomieq.sd(<2 x double>, <2 x double>)
537 declare i32 @llvm.x86.sse2.ucomige.sd(<2 x double>, <2 x double>)
[all …]
H A Dx86-sse2.ll12 %3 = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %2)
23 %3 = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %2)
529 declare i32 @llvm.x86.sse2.comieq.sd(<2 x double>, <2 x double>)
530 declare i32 @llvm.x86.sse2.comige.sd(<2 x double>, <2 x double>)
531 declare i32 @llvm.x86.sse2.comigt.sd(<2 x double>, <2 x double>)
532 declare i32 @llvm.x86.sse2.comile.sd(<2 x double>, <2 x double>)
533 declare i32 @llvm.x86.sse2.comilt.sd(<2 x double>, <2 x double>)
534 declare i32 @llvm.x86.sse2.comineq.sd(<2 x double>, <2 x double>)
536 declare i32 @llvm.x86.sse2.ucomieq.sd(<2 x double>, <2 x double>)
537 declare i32 @llvm.x86.sse2.ucomige.sd(<2 x double>, <2 x double>)
[all …]
H A Dx86-vec_demanded_elts.ll40 ; CHECK-NEXT: [[TMP4:%.*]] = tail call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> [[V41]])
42 ; CHECK-NEXT: [[TMP5:%.*]] = tail call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> [[V51]])
44 ; CHECK-NEXT: [[TMP6:%.*]] = tail call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> [[V61]])
79 %tmp4 = tail call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %v41)
82 %tmp5 = tail call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %v51)
85 %tmp6 = tail call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %v61)
88 %tmp7 = tail call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %v71)
108 declare i32 @llvm.x86.sse2.cvtsd2si(<2 x double>)
109 declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>)
110 declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>)
[all …]
H A Dx86-vec_demanded_elts-inseltpoison.ll42 ; CHECK-NEXT: [[TMP4:%.*]] = tail call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> [[V41]])
44 ; CHECK-NEXT: [[TMP5:%.*]] = tail call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> [[V51]])
46 ; CHECK-NEXT: [[TMP6:%.*]] = tail call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> [[V61]])
81 %tmp4 = tail call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %v41)
84 %tmp5 = tail call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %v51)
87 %tmp6 = tail call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %v61)
90 %tmp7 = tail call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %v71)
110 declare i32 @llvm.x86.sse2.cvtsd2si(<2 x double>)
111 declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>)
112 declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dvec_shift5.ll190 %a = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> undef, i32 6)
192 %res = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> undef, i32 7)
211 %a = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> undef, i32 3)
217 declare <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16>, i32)
218 declare <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16>, i32)
219 declare <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16>, i32)
220 declare <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32>, i32)
221 declare <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32>, i32)
222 declare <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32>, i32)
223 declare <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64>, i32)
[all …]
H A Dfptosi-constant.ll11 %r = call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> <double 5.0e+09, double undef>)
20 %r = call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> <double 5.0e+09, double undef>)
29 %r = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> <double 5.0e+19, double undef>)
116 declare i32 @llvm.x86.sse2.cvtsd2si(<2 x double>)
117 declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>)
119 declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>)
120 declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>)
122 declare <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double>)
123 declare <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double>)
131 declare <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float>)
[all …]
H A Dvec_shift.ll2 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X86
3 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X64
13 …%tmp9 = tail call <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> %tmp8, <8 x i16> %tmp6 ) nounwind rea…
34 …%tmp9 = tail call <8 x i16> @llvm.x86.sse2.psra.w( <8 x i16> %tmp2, <8 x i16> %tmp8 ) ; <<8 x i16…
39 declare <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16>, <8 x i16>) nounwind readnone
47 …%tmp9 = tail call <2 x i64> @llvm.x86.sse2.psrl.q( <2 x i64> %b1, <2 x i64> %c ) nounwind readnone…
51 declare <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64>, <2 x i64>) nounwind readnone
53 declare <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16>, <8 x i16>) nounwind readnone
H A Dvec_shift2.ll2 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s
3 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s
11 …%tmp2 = tail call <8 x i16> @llvm.x86.sse2.psrl.w( <8 x i16> %tmp1, <8 x i16> bitcast (<4 x i32> <…
24 …%tmp2 = tail call <4 x i32> @llvm.x86.sse2.psll.d( <4 x i32> %tmp1, <4 x i32> < i32 14, i32 undef,…
28 declare <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16>, <8 x i16>) nounwind readnone
29 declare <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32>, <4 x i32>) nounwind readnone
H A Dsse2-intrinsics-x86.ll251 %cvt = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> %a0)
292 %cvt = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> %a0)
555 %cvt = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> %a0)
1644 tail call void @llvm.x86.sse2.pause()
1647 declare void @llvm.x86.sse2.pause() nounwind
1654 tail call void @llvm.x86.sse2.lfence()
1657 declare void @llvm.x86.sse2.lfence() nounwind
1664 tail call void @llvm.x86.sse2.mfence()
1667 declare void @llvm.x86.sse2.mfence() nounwind
1680 tail call void @llvm.x86.sse2.clflush(ptr %p)
[all …]
H A Dvec_shift3.ll2 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X86
3 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X64
18 …%tmp3 = tail call <2 x i64> @llvm.x86.sse2.pslli.q( <2 x i64> %x1, i32 %bits ) nounwind readnone …
28 …%tmp3 = tail call <2 x i64> @llvm.x86.sse2.pslli.q( <2 x i64> %x1, i32 10 ) nounwind readnone ; …
46 …%tmp4 = tail call <8 x i16> @llvm.x86.sse2.psrai.w( <8 x i16> %tmp2, i32 %bits ) nounwind readnone…
51 declare <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16>, i32) nounwind readnone
52 declare <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64>, i32) nounwind readnone
H A Dsse2-intrinsics-fast-isel-x86_64.ll2 ; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-pref…
6 ; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/sse2-builtins.c
18 %res = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %a0)
21 declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>) nounwind readnone
47 %res = call <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double> %a0, i64 %a1)
50 declare <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double>, i64) nounwind readnone
77 %res = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %a0)
80 declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) nounwind readnone
H A D2007-05-17-ShuffleISelBug.ll1 ; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 | FileCheck %s
5 declare <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16>, <8 x i16>)
7 declare <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16>, <8 x i16>)
16 …%tmp838 = tail call <8 x i16> @llvm.x86.sse2.psrl.w( <8 x i16> %tmp832, <8 x i16> < i16 8, i16 und…
17 …%tmp1020 = tail call <16 x i8> @llvm.x86.sse2.packuswb.128( <8 x i16> zeroinitializer, <8 x i16> %…
H A Dpsadbw.ll2 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X86
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,…
11 %3 = tail call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> %0, <16 x i8> %1)
32 %5 = tail call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> %3, <16 x i8> %4)
37 declare <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8>, <16 x i8>)
H A Dpic-load-remat.ll2 ; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 -relocation-model=pic | FileCheck %s
26 …%tmp4609 = tail call <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> zeroinitializer, <8 x i16> bitcast…
28 …%tmp4658 = tail call <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> %tmp4651, <8 x i16> bitcast (<4 x …
29 …%tmp4669 = tail call <8 x i16> @llvm.x86.sse2.pavg.w( <8 x i16> < i16 -23170, i16 -23170, i16 -231…
35 …%tmp4779 = tail call <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> %tmp4772, <8 x i16> bitcast (<4 x …
39 …%tmp4900 = tail call <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> zeroinitializer, <8 x i16> bitcast…
40 …%tmp4911 = tail call <8 x i16> @llvm.x86.sse2.pavg.w( <8 x i16> < i16 -23170, i16 -23170, i16 -231…
57 declare <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16>, <8 x i16>) nounwind readnone
59 declare <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16>, <8 x i16>) nounwind readnone
H A Dsse-cvttp2si.ll9 declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>)
10 declare <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double>)
13 declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>)
14 declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>)
101 %fptosi = tail call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %x)
119 %fptosi = tail call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %x)
137 %fptosi = tail call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %x)
155 %fptosi = tail call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %x)
173 %fptosi = tail call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %x)
190 %fptosi = tail call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %x)
[all …]
H A Dsse2-intrinsics-x86-upgrade.ll28 declare <2 x double> @llvm.x86.sse2.sqrt.pd(<2 x double>) nounwind readnone
49 declare <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double>) nounwind readnone
165 declare <2 x i64> @llvm.x86.sse2.psll.dq(<2 x i64>, i32) nounwind readnone
189 declare <2 x i64> @llvm.x86.sse2.psrl.dq(<2 x i64>, i32) nounwind readnone
210 declare <2 x double> @llvm.x86.sse2.cvtdq2pd(<4 x i32>) nounwind readnone
267 call void @llvm.x86.sse2.storel.dq(ptr %a0, <4 x i32> %a1)
270 declare void @llvm.x86.sse2.storel.dq(ptr, <4 x i32>) nounwind
320 call void @llvm.x86.sse2.storeu.dq(ptr %a0, <16 x i8> %a2)
323 declare void @llvm.x86.sse2.storeu.dq(ptr, <16 x i8>) nounwind
391 call void @llvm.x86.sse2.storeu.pd(ptr %a0, <2 x double> %a2)
[all …]
H A Dsse2-intrinsics-x86_64.ll2 ; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=-avx,+sse2 -show-mc-encoding …
21 %res = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %a0) ; <i64> [#uses=1]
24 declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>) nounwind readnone
42 %res = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %a0) ; <i64> [#uses=1]
45 declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) nounwind readnone
H A Dfast-isel-sse12-fptoint.ll1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx,+sse2 -fast-isel -fast-isel-abort=1 | File…
39 %3 = call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %2)
42 declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>) nounwind readnone
51 %3 = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %2)
54 declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) nounwind readnone
H A Dmaskmovdqu.ll2 ; RUN: llc < %s -mtriple=i686-- -mattr=+sse2,-avx | FileCheck %s --check-prefix=i686_SSE2
3 ; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2,-avx | FileCheck %s --check-prefix=x86_64_SSE2
4 ; RUN: llc < %s -mtriple=x86_64--gnux32 -mattr=+sse2,-avx | FileCheck %s --check-prefix=x86_x32_SSE2
52 tail call void @llvm.x86.sse2.maskmov.dqu( <16 x i8> %a, <16 x i8> %b, ptr %c )
56 declare void @llvm.x86.sse2.maskmov.dqu(<16 x i8>, <16 x i8>, ptr) nounwind
/llvm-project-15.0.7/llvm/test/Instrumentation/MemorySanitizer/
H A Dsse2-intrinsics-x86.ll1333 ; CHECK-NEXT: tail call void @llvm.x86.sse2.pause()
1336 tail call void @llvm.x86.sse2.pause()
1339 declare void @llvm.x86.sse2.pause() nounwind
1344 ; CHECK-NEXT: tail call void @llvm.x86.sse2.lfence()
1347 tail call void @llvm.x86.sse2.lfence()
1350 declare void @llvm.x86.sse2.lfence() nounwind
1355 ; CHECK-NEXT: tail call void @llvm.x86.sse2.mfence()
1358 tail call void @llvm.x86.sse2.mfence()
1361 declare void @llvm.x86.sse2.mfence() nounwind
1376 tail call void @llvm.x86.sse2.clflush(i8* %p)
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/ConstProp/
H A Dsse.ll53 %i2 = call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %dm) nounwind
54 %i3 = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %dm) nounwind
74 %i2 = call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %dm) nounwind
75 %i3 = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %dm) nounwind
95 %i2 = call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %dm) nounwind
96 %i3 = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %dm) nounwind
150 %i2 = call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %dm) nounwind
171 %i2 = call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %dm) nounwind
192 %i2 = call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %dm) nounwind
205 declare i32 @llvm.x86.sse2.cvtsd2si(<2 x double>) nounwind readnone
[all …]
/llvm-project-15.0.7/llvm/include/llvm/Support/
H A DX86TargetParser.def113 X86_FEATURE_COMPAT(SSE2, "sse2", 3)
229 CPU_SPECIFIC("pentium_4", "pentium4", 'J', "+cmov,+mmx,+sse,+sse2")
230 CPU_SPECIFIC("pentium_m", "pentium-m", 'K', "+cmov,+mmx,+sse,+sse2")
231 CPU_SPECIFIC("pentium_4_sse3", "prescott", 'L', "+cmov,+mmx,+sse,+sse2,+sse3")
232 CPU_SPECIFIC("core_2_duo_ssse3", "core2", 'M', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3")
233 CPU_SPECIFIC("core_2_duo_sse4_1", "penryn", 'N', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1")
234 CPU_SPECIFIC("atom", "atom", 'O', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+movbe")
235 CPU_SPECIFIC("atom_sse4_2", "silvermont", 'c', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,…
236 CPU_SPECIFIC("core_i7_sse4_2", "nehalem", 'P', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,…
237 CPU_SPECIFIC("core_aes_pclmulqdq", "westmere", 'Q', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+ss…
[all …]
/llvm-project-15.0.7/llvm/test/Other/
H A Dopt-override-mcpu-mattr.ll7 …sp uwtable "target-cpu"="broadwell" "target-features"="+ssse3,+cx16,+sse,+sse2,+sse3,+avx2" "use-s…
8 …ne ssp uwtable "target-cpu"="core2" "target-features"="+ssse3,+cx16,+sse,+sse2,+sse3,+avx2" "use-s…
20 attributes #0 = { nounwind readnone ssp uwtable "target-features"="+ssse3,+cx16,+sse,+sse2,+sse3" "…
21 …ne ssp uwtable "target-cpu"="core2" "target-features"="+ssse3,+cx16,+sse,+sse2,+sse3" "use-soft-fl…
/llvm-project-15.0.7/llvm/test/CodeGen/X86/GlobalISel/
H A Dfconstant.ll2 ; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -global-isel -verify-machin…
3 ; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -global-isel -code-model=large -verify-machin…
4 ; RUN: llc -mtriple=i386-linux-gnu -mattr=+sse2 -global-isel -verify-machin…
5 ; RUN: llc -mtriple=i386-linux-gnu -mattr=+sse2 -global-isel -code-model=large -verify-machin…
6 ; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -global-isel -relocation-model=pic -verify-machin…
/llvm-project-15.0.7/llvm/test/Transforms/RewriteStatepointsForGC/X86/
H A Dintrinsic-attributes.ll4 ; CHECK: declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>)
5 declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>)
8 %ret = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %arg)

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