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Searched refs:srshr (Results 1 – 22 of 22) sorted by relevance

/llvm-project-15.0.7/llvm/test/MC/AArch64/SVE2/
H A Dsrshr-diagnostics.s3 srshr z18.b, p0/m, z18.b, #0 label
8 srshr z1.b, p0/m, z1.b, #9 label
13 srshr z21.h, p0/m, z21.h, #0 label
18 srshr z14.h, p0/m, z14.h, #17 label
23 srshr z6.s, p0/m, z6.s, #0 label
33 srshr z3.d, p0/m, z3.d, #0 label
47 srshr z0.b, p0/m, z1.b, #1 label
56 srshr z0.b, p0/m, z0.d, #1 label
61 srshr z0.d, p0/m, z0.b, #1 label
70 srshr z0.b, p0/z, z0.b, #1 label
[all …]
H A Dsrshr.s12 srshr z0.b, p0/m, z0.b, #1 label
18 srshr z31.b, p0/m, z31.b, #8 label
24 srshr z0.h, p0/m, z0.h, #1 label
30 srshr z31.h, p0/m, z31.h, #16 label
36 srshr z0.s, p0/m, z0.s, #1 label
42 srshr z31.s, p0/m, z31.s, #32 label
48 srshr z0.d, p0/m, z0.d, #1 label
54 srshr z31.d, p0/m, z31.d, #64 label
70 srshr z31.d, p0/m, z31.d, #64 label
82 srshr z31.d, p0/m, z31.d, #64 label
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve2-rsra.ll60 …%shift = call <vscale x 16 x i8> @llvm.aarch64.sve.srshr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x…
71 …%shift = call <vscale x 8 x i16> @llvm.aarch64.sve.srshr.nxv8i16(<vscale x 8 x i1> %pg, <vscale x …
82 …%shift = call <vscale x 4 x i32> @llvm.aarch64.sve.srshr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x …
93 …%shift = call <vscale x 2 x i64> @llvm.aarch64.sve.srshr.nxv2i64(<vscale x 2 x i1> %pg, <vscale x …
109 declare <vscale x 16 x i8> @llvm.aarch64.sve.srshr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, …
110 declare <vscale x 8 x i16> @llvm.aarch64.sve.srshr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, i…
111 declare <vscale x 4 x i32> @llvm.aarch64.sve.srshr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i…
112 declare <vscale x 2 x i64> @llvm.aarch64.sve.srshr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i…
H A Dsve2-intrinsics-uniform-dsp.ll1425 ; CHECK-NEXT: srshr z0.b, p0/m, z0.b, #8
1427 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.srshr.nxv16i8(<vscale x 16 x i1> %pg,
1436 ; CHECK-NEXT: srshr z0.h, p0/m, z0.h, #1
1438 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.srshr.nxv8i16(<vscale x 8 x i1> %pg,
1447 ; CHECK-NEXT: srshr z0.s, p0/m, z0.s, #22
1449 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.srshr.nxv4i32(<vscale x 4 x i1> %pg,
1458 ; CHECK-NEXT: srshr z0.d, p0/m, z0.d, #54
1460 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.srshr.nxv2i64(<vscale x 2 x i1> %pg,
2790 declare <vscale x 8 x i16> @llvm.aarch64.sve.srshr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, i…
2791 declare <vscale x 4 x i32> @llvm.aarch64.sve.srshr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i…
[all …]
H A Darm64-vshift.ll742 ;CHECK: srshr.8b
750 ;CHECK: srshr.4h
758 ;CHECK: srshr.2s
766 ;CHECK: srshr.16b
774 ;CHECK: srshr.8h
782 ;CHECK: srshr.4s
790 ;CHECK: srshr.2d
798 ;CHECK: srshr {{d[0-9]+}}, {{d[0-9]+}}, #1
806 ;CHECK: srshr {{d[0-9]+}}, {{d[0-9]+}}, #1
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Dneon-simd-shift.s83 srshr v0.8b, v1.8b, #3
84 srshr v0.4h, v1.4h, #3
85 srshr v0.2s, v1.2s, #3
86 srshr v0.16b, v1.16b, #3
87 srshr v0.8h, v1.8h, #3
88 srshr v0.4s, v1.4s, #3
89 srshr v0.2d, v1.2d, #3
H A Dneon-scalar-shift-imm.s22 srshr d19, d18, #7
H A Darm64-advsimd.s1375 srshr d0, d0, #1 define
1531 srshr.8b v0, v0, #1
1532 srshr.16b v0, v0, #2
1533 srshr.4h v0, v0, #3
1534 srshr.8h v0, v0, #4
1535 srshr.2s v0, v0, #5
1536 srshr.4s v0, v0, #6
1537 srshr.2d v0, v0, #7
1703 ; CHECK: srshr.8b v0, v0, #1 ; encoding: [0x00,0x24,0x0f,0x0f]
1705 ; CHECK: srshr.4h v0, v0, #3 ; encoding: [0x00,0x24,0x1d,0x0f]
[all …]
H A Dneon-diagnostics.s1515 srshr v0.8b, v1.8h, #3
1516 srshr v0.4h, v1.4s, #3
1517 srshr v0.2s, v1.2d, #3
1518 srshr v0.16b, v1.16b, #9
1519 srshr v0.8h, v1.8h, #17
1520 srshr v0.4s, v1.4s, #33
1521 srshr v0.2d, v1.2d, #65
4873 srshr d19, d18, #99
/llvm-project-15.0.7/clang/test/CodeGen/arm-mve-intrinsics/
H A Dscalar-shifts.c130 return srshr(value, 6); in test_srshr()
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/mve-intrinsics/
H A Dscalar-shifts.ll134 ; CHECK-NEXT: srshr r0, #6
137 %0 = call i32 @llvm.arm.mve.srshr(i32 %value, i32 6)
141 declare i32 @llvm.arm.mve.srshr(i32, i32)
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dmve-scalar-shift.s130 # CHECK: srshr lr, #11 @ encoding: [0x5e,0xea,0xef,0x2f]
132 srshr lr, #11 label
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dmve-scalar-shift.txt46 # CHECK: srshr lr, #11 @ encoding: [0x5e,0xea,0xef,0x2f]
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Cortex/
H A DA55-neon-instructions.s703 srshr d19, d18, #7 label
704 srshr v0.16b, v0.16b, #3 label
705 srshr v0.2d, v0.2d, #3 label
706 srshr v0.2s, v0.2s, #3 label
707 srshr v0.4h, v0.4h, #3 label
708 srshr v0.4s, v0.4s, #3 label
709 srshr v0.8b, v0.8b, #3 label
710 srshr v0.8h, v0.8h, #3 label
1772 # CHECK-NEXT: 1 3 0.50 srshr d19, d18, #7
1774 # CHECK-NEXT: 1 3 1.00 srshr v0.2d, v0.2d, #3
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Neoverse/
H A DN2-neon-instructions.s703 srshr d19, d18, #7 label
704 srshr v0.16b, v0.16b, #3 label
705 srshr v0.2d, v0.2d, #3 label
706 srshr v0.2s, v0.2s, #3 label
707 srshr v0.4h, v0.4h, #3 label
708 srshr v0.4s, v0.4s, #3 label
709 srshr v0.8b, v0.8b, #3 label
710 srshr v0.8h, v0.8h, #3 label
1772 # CHECK-NEXT: 1 2 0.50 srshr d19, d18, #7
1774 # CHECK-NEXT: 1 4 1.00 srshr v0.2d, v0.2d, #3
[all …]
H A DN2-sve-instructions.s3057 srshr z0.b, p0/m, z0.b, #1 label
3058 srshr z0.d, p0/m, z0.d, #1 label
3059 srshr z0.h, p0/m, z0.h, #1 label
3060 srshr z0.s, p0/m, z0.s, #1 label
3061 srshr z31.b, p0/m, z31.b, #8 label
3062 srshr z31.d, p0/m, z31.d, #64 label
3063 srshr z31.h, p0/m, z31.h, #16 label
3064 srshr z31.s, p0/m, z31.s, #32 label
6984 # CHECK-NEXT: 1 4 1.00 srshr z0.b, p0/m, z0.b, #1
6985 # CHECK-NEXT: 1 4 1.00 srshr z0.d, p0/m, z0.d, #1
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AArch64/
H A Dneon-instructions.txt792 # CHECK: srshr v0.8b, v1.8b, #3
793 # CHECK: srshr v0.4h, v1.4h, #3
794 # CHECK: srshr v0.2s, v1.2s, #3
795 # CHECK: srshr v0.16b, v1.16b, #3
796 # CHECK: srshr v0.8h, v1.8h, #3
797 # CHECK: srshr v0.4s, v1.4s, #3
798 # CHECK: srshr v0.2d, v1.2d, #3
1828 # CHECK: srshr d19, d18, #7
H A Darm64-advsimd.txt1830 # CHECK: srshr d0, d0, #0x3f
2106 # CHECK: srshr.8b v0, v0, #0x7
2107 # CHECK: srshr.16b v0, v0, #0x6
2108 # CHECK: srshr.4h v0, v0, #0xd
2109 # CHECK: srshr.8h v0, v0, #0xc
2110 # CHECK: srshr.2s v0, v0, #0x1b
2111 # CHECK: srshr.4s v0, v0, #0x1a
2112 # CHECK: srshr.2d v0, v0, #0x39
/llvm-project-15.0.7/clang/include/clang/Basic/
H A Darm_mve.td1251 defm srshr: ScalarSaturatingShiftImm<s32, s64>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td6625 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", AArch64srshri>;
6677 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", AArch64srshri>;
H A DAArch64SVEInstrInfo.td3242 …defm SRSHR_ZPmI : sve_int_bin_pred_shift_imm_right< 0b1100, "srshr", "SRSHR_ZPZI", int_aarch6…
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrMVE.td475 def MVE_SRSHR : MVE_ScalarShiftSRegImm<"srshr", 0b10>;