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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrAMX.td65 TILE:$src4), []>;
110 let isPseudo = true, Constraints = "$src4 = $dst" in {
112 GR16:$src2, GR16:$src3, TILE:$src4,
116 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
118 GR16:$src2, GR16:$src3, TILE:$src4,
124 GR16:$src2, GR16:$src3, TILE:$src4,
128 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
130 GR16:$src2, GR16:$src3, TILE:$src4,
169 let isPseudo = true, Constraints = "$src4 = $dst" in
171 GR16:$src2, GR16:$src3, TILE:$src4,
[all …]
H A DX86InstrXOP.td421 (ins RC:$src1, RC:$src2, RC:$src3, u4imm:$src4),
423 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
425 (VT (X86vpermil2 RC:$src1, RC:$src2, RC:$src3, (i8 timm:$src4))))]>,
428 (ins RC:$src1, RC:$src2, intmemop:$src3, u4imm:$src4),
430 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
433 (i8 timm:$src4))))]>, VEX_W,
436 (ins RC:$src1, fpmemop:$src2, RC:$src3, u4imm:$src4),
438 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
441 RC:$src3, (i8 timm:$src4))))]>,
450 (ins RC:$src1, RC:$src2, RC:$src3, u4imm:$src4),
[all …]
H A DX86InstrAVX512.td11826 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src4",
11834 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src4",
11875 _.RC:$src2, (i8 timm:$src4)),
11884 _.RC:$src2, (i8 timm:$src4)),
11902 _.RC:$src1, (i8 timm:$src4)),
11921 (VPTERNLOG321_imm8 timm:$src4))>;
11929 (VPTERNLOG132_imm8 timm:$src4))>;
12092 OpcodeStr#_.Suffix, "$src4, $src3, $src2", "$src2, $src3, $src4",
12099 OpcodeStr#_.Suffix, "$src4, $src3, $src2", "$src2, $src3, $src4",
12141 OpcodeStr#_.Suffix, "$src4, $src3, $src2", "$src2, $src3, $src4",
[all …]
/llvm-project-15.0.7/flang/test/Evaluate/
H A Dtest_folding.py71 src4 = "" variable
108 src4 += f"{line}\n"
134 if src4 or warning_diffs:
139 if src4:
140 for line in src4.split("\n"):
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonMapAsm2IntrinV62.gen.td114 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4),
115 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
117 HvxVR:$src3, imm:$src4),
118 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
122 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4),
123 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
125 HvxVR:$src3, imm:$src4),
126 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
H A DHexagonIntrinsicsV60.td271 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4),
272 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>;
275 IntRegs:$src3, imm:$src4),
276 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>;
280 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4),
281 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
284 HvxVR:$src3, IntRegs:$src4),
285 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
289 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4),
293 HvxVR:$src3, IntRegs:$src4),
[all …]
H A DHexagonDepMapAsm2Intrin.td612 def: Pat<(int_hexagon_F2_sffma_sc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3, PredRegs:$src4),
2417 def: Pat<(int_hexagon_V6_vlutvvb_oracc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4),
2425 def: Pat<(int_hexagon_V6_vlutvwh_oracc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4),
3307 def: Pat<(int_hexagon_V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),
3309 def: Pat<(int_hexagon_V6_vscattermh_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),
3311 def: Pat<(int_hexagon_V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),
3319 def: Pat<(int_hexagon_V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4),
3323 def: Pat<(int_hexagon_V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4),
3331 def: Pat<(int_hexagon_V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),
3333 def: Pat<(int_hexagon_V6_vscattermw_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4),
[all …]
H A DHexagonIntrinsicsV5.td184 IntRegs:$src3, u2_0ImmPred:$src4),
186 IntRegs:$src3, u2_0ImmPred:$src4)>;
H A DHexagonIntrinsics.td145 : Pat <(IntID I32:$src1, I32:$src2, u4_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4),
147 (XformImm u5_0ImmPred:$src4))>;
/llvm-project-15.0.7/lldb/test/API/tools/lldb-vscode/step/
H A DTestVSCode_step.py69 (src4, line4) = self.get_source_and_line(threadId=tid)
72 self.assertEqual(src1, src4, 'verify step over source')
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dswp-prolog-phi4.ll11 %add.ptr3.pn = phi i8* [ undef, %entry ], [ %src4.0394, %for.end ]
13 %src4.0394 = getelementptr inbounds i8, i8* %add.ptr3.pn, i32 %srcStride
32 %arrayidx94.epil = getelementptr inbounds i8, i8* %src4.0394, i32 %add17.epil
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dpr53357.ll77 define i32 @src4(i32 %0, i32 %1) {
78 ; CHECK-LABEL: @src4(
/llvm-project-15.0.7/llvm/test/TableGen/
H A DGlobalISelEmitter.td276 // R19N-NEXT: // MIs[1] src4
287 …src4, (complex:{ *:[i32] } i32imm:{ *:[i32] }:$src5a, i32imm:{ *:[i32] }:$src5b))) => (INSN3:{ *…
317 (ins GPR32:$src3, complex:$src4, i32imm:$src5a, i32imm:$src5b), []>;
320 complex:$src4,
323 (INSN4 GPR32:$src3, complex:$src4, i32imm:$src5a,
499 // R00N-NEXT: // MIs[2] src4
506 … *:[i32] }:$src4)) => (INSNBOB:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2, GPR32…
512 // R00C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src4
526 def INSNBOB : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3, GPR32:$src4),
528 (sub (sub GPR32:$src1, GPR32:$src2), (sub GPR32:$src3, GPR32:$src4)))]>,
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/X86/
H A Dshuffle-broadcast.ll274 define void @test_vXi1(<2 x i1> %src2, <4 x i1> %src4, <8 x i1> %src8, <16 x i1> %src16, <32 x i1> …
277 …und an estimated cost of 1 for instruction: %V4 = shufflevector <4 x i1> %src4, <4 x i1> undef, <4…
286 …und an estimated cost of 1 for instruction: %V4 = shufflevector <4 x i1> %src4, <4 x i1> undef, <4…
295 …und an estimated cost of 1 for instruction: %V4 = shufflevector <4 x i1> %src4, <4 x i1> undef, <4…
304 …und an estimated cost of 1 for instruction: %V4 = shufflevector <4 x i1> %src4, <4 x i1> undef, <4…
313 …und an estimated cost of 1 for instruction: %V4 = shufflevector <4 x i1> %src4, <4 x i1> undef, <4…
322 …und an estimated cost of 5 for instruction: %V4 = shufflevector <4 x i1> %src4, <4 x i1> undef, <4…
330 %V4 = shufflevector <4 x i1> %src4, <4 x i1> undef, <4 x i32> zeroinitializer
/llvm-project-15.0.7/libc/test/src/__support/File/
H A Dfile_test.cpp415 MemoryView src4(initial_content, READ_SIZE), dst4(read_data, READ_SIZE); in TEST() local
416 EXPECT_MEM_EQ(src4, dst4); in TEST()
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.td2604 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2608 "\t[$addr], {{$src1, $src2, $src3, $src4}};", []>;
2611 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2615 "\t[$addr], {{$src1, $src2, $src3, $src4}};", []>;
2618 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2622 "\t[$addr], {{$src1, $src2, $src3, $src4}};", []>;
2625 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2629 "\t[$addr+$offset], {{$src1, $src2, $src3, $src4}};", []>;
2632 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2636 "\t[$addr+$offset], {{$src1, $src2, $src3, $src4}};", []>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td528 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4),
529 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", []>;
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrNEON.td1290 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
1293 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>,
1332 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1335 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
2067 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
2068 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
2087 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
2088 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
2385 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
2425 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DBUFInstructions.td1586 …(ops node:$src0, node:$src1, node:$src2, node:$src3, node:$src4, node:$src5, node:$src6, node:$src…
1587 (vt (Op $src0, $src1, $src2, $src3, $src4, $src5, $src6, $src7)),