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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonDepMapAsm2Intrin.td1905 def: Pat<(int_hexagon_V6_vaddbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),
1909 def: Pat<(int_hexagon_V6_vaddbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),
1921 def: Pat<(int_hexagon_V6_vaddhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),
1925 def: Pat<(int_hexagon_V6_vaddhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),
1973 def: Pat<(int_hexagon_V6_vaddwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),
1977 def: Pat<(int_hexagon_V6_vaddwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),
2649 def: Pat<(int_hexagon_V6_vmux HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),
2869 def: Pat<(int_hexagon_V6_vsubbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),
2885 def: Pat<(int_hexagon_V6_vsubhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),
2937 def: Pat<(int_hexagon_V6_vsubwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),
[all …]
H A DHexagonMapAsm2IntrinV62.gen.td39 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),
40 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
42 HvxVR:$src3),
43 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
55 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
58 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
63 (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
106 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, imm:$src3),
107 (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>;
109 imm:$src3),
[all …]
H A DHexagonIntrinsicsV60.td207 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),
211 HvxVR:$src3),
212 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>;
216 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),
220 HvxVR:$src3),
221 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
230 (MI HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>;
253 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, imm:$src3),
254 (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>;
258 (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>;
[all …]
H A DHexagonIntrinsics.td146 (OutputInst I32:$src1, I32:$src2, u4_0ImmPred:$src3,
207 def : Pat<(IntID HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),
208 (MI HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>,
212 HvxVR:$src3),
213 (MI HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>,
310 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3),
315 u3_0ImmPred:$src3),
335 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),
336 (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>,
340 IntRegs:$src3),
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrXOP.td174 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
181 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
287 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
295 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
303 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
318 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
334 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
343 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
349 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
363 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[all …]
H A DX86InstrFMA.td42 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
50 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
63 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
70 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
83 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
184 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
192 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
205 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
397 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
404 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[all …]
H A DX86InstrAMX.td93 "tdpbssd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
97 "tdpbsud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
101 "tdpbusd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
105 "tdpbuud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
141 u8imm:$src2, u8imm:$src3),
143 timm:$src2, timm:$src3)]>;
145 u8imm:$src2, u8imm:$src3),
147 timm:$src2, timm:$src3)]>;
149 u8imm:$src2, u8imm:$src3),
153 u8imm:$src2, u8imm:$src3),
[all …]
H A DX86InstrFragmentsSIMD.td201 def X86any_cmpp : PatFrags<(ops node:$src1, node:$src2, node:$src3),
220 def X86any_cmpm : PatFrags<(ops node:$src1, node:$src2, node:$src3),
547 def X86any_Fmsub : PatFrags<(ops node:$src1, node:$src2, node:$src3),
1104 def masked_load : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1129 def masked_store : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1160 PatFrag<(ops node:$src1, node:$src2, node:$src3),
1161 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1165 PatFrag<(ops node:$src1, node:$src2, node:$src3),
1166 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1170 PatFrag<(ops node:$src1, node:$src2, node:$src3),
[all …]
H A DX86InstrSSE.td3973 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
3982 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
5556 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5566 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5944 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5953 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5971 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5980 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6128 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6137 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[all …]
H A DX86InstrAVX512.td1772 OpcodeStr, "$src3, $src2", "$src2, $src3",
1779 OpcodeStr, "$src3, $src2", "$src2, $src3",
1894 OpcodeStr, "$src3, $src2", "$src2, $src3",
1900 OpcodeStr, "$src3, $src2", "$src2, $src3",
6766 OpcodeStr, "$src3, $src2", "$src2, $src3",
6773 OpcodeStr, "$src3, $src2", "$src2, $src3",
6859 OpcodeStr, "$src3, $src2", "$src2, $src3",
6866 OpcodeStr, "$src3, $src2", "$src2, $src3",
6953 OpcodeStr, "$src3, $src2", "$src2, $src3",
12387 "$src3, $src2", "$src2, $src3",
[all …]
H A DX86InstrShiftRotate.td697 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
704 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
711 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
718 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
725 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
732 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
771 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
777 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
784 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
790 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[all …]
H A DX86InstrMMX.td111 (ins VR64:$src1, VR64:$src2, u8imm:$src3),
112 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
113 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 timm:$src3)))]>,
116 (ins VR64:$src1, i64mem:$src2, u8imm:$src3),
117 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
119 (i8 timm:$src3)))]>,
526 (ins VR64:$src1, GR32orGR64:$src2, i32u8imm:$src3),
527 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
534 (ins VR64:$src1, i16mem:$src2, i32u8imm:$src3),
535 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DEXPInstructions.td16 ExpSrc0:$src0, ExpSrc1:$src1, ExpSrc2:$src2, ExpSrc3:$src3,
37 : EXPCommon<0, done, "exp$tgt $src0, $src1, $src2, $src3"
45 : EXPCommon<row, done, "exp$tgt $src0, $src1, $src2, $src3"
131 (vt ExpSrc2:$src2), (vt ExpSrc3:$src3),
134 ExpSrc2:$src2, ExpSrc3:$src3, timm:$vm, 0, timm:$en)
140 (vt ExpSrc2:$src2), (vt ExpSrc3:$src3),
143 ExpSrc2:$src2, ExpSrc3:$src3, 0, 0, timm:$en)
/llvm-project-15.0.7/clang/test/SemaOpenCL/
H A Dqueue_t_overload.cl6 void kernel ker(__local char *src1, __local float *src2, __global int *src3) {
10 foo(q, src3); // expected-error {{no matching function for call to 'foo'}}
11 foo(1, src3); // expected-error {{no matching function for call to 'foo'}}
H A Devent_t_overload.cl6 void kernel ker(__local char *src1, __local float *src2, __global int *src3) {
10 foo(evt, src3); // expected-error {{no matching function for call to 'foo'}}
/llvm-project-15.0.7/llvm/test/TableGen/
H A Dusevalname.td19 def rri : Instr<[(set RC:$dst, (shufp:$src3
23 // CHECK: shufp:src3
H A DGlobalISelEmitter.td271 // R19N-NEXT: // MIs[1] src3
291 // R19C-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src3
319 (select GPR32:$src3,
323 (INSN4 GPR32:$src3, complex:$src4, i32imm:$src5a,
359 // R21N-NEXT: // MIs[0] src3
446 def : Pat<(frag GPR32:$src1, complex:$src2, complex:$src3),
447 (INSN2 GPR32:$src1, complex:$src3, complex:$src2)>;
495 // R00N-NEXT: // MIs[2] src3
769 // NOOPT-NEXT: // MIs[0] src3
794 // NOOPT-NEXT: // MIs[0] src3
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dllvm.amdgcn.alignbyte.ll7 define amdgpu_kernel void @v_alignbyte_b32(i32 addrspace(1)* %out, i32 %src1, i32 %src2, i32 %src3)…
8 %val = call i32 @llvm.amdgcn.alignbyte(i32 %src1, i32 %src2, i32 %src3) #0
H A Dllvm.amdgcn.perm.ll8 define amdgpu_ps void @v_perm_b32_v_v_v(i32 %src1, i32 %src2, i32 %src3, i32 addrspace(1)* %out) #1…
9 %val = call i32 @llvm.amdgcn.perm(i32 %src1, i32 %src2, i32 %src3) #0
/llvm-project-15.0.7/flang/test/Evaluate/
H A Dtest_folding.py70 src3 = "" variable
103 src3 += f"{m.string}\n"
105 for passed_results, line in enumerate(src3.split("\n")):
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dmve-fmas.ll46 %0 = fmul <8 x half> %src2, %src3
91 %0 = fmul <8 x half> %src2, %src3
136 %0 = fmul <8 x half> %src2, %src3
182 %src3 = fptrunc float %src3o to half
239 %src3 = fptrunc float %src3o to half
267 %0 = fmul <4 x float> %src2, %src3
292 %0 = fmul <4 x float> %src2, %src3
317 %0 = fmul <4 x float> %src2, %src3
477 %0 = fmul <8 x half> %src2, %src3
574 %0 = fmul <8 x half> %src2, %src3
[all …]
/llvm-project-15.0.7/libc/test/src/__support/File/
H A Dfile_test.cpp195 MemoryView src3("hello\n file\0longer for an \n overflow", 37), in TEST() local
197 EXPECT_MEM_EQ(src3, dst_full_final); in TEST()
204 EXPECT_MEM_EQ(src3, dst_line_final); in TEST()
205 EXPECT_MEM_EQ(src3, dst_full_final); in TEST()
265 MemoryView src3(initial_content, READ_SIZE), dst3(read_data, READ_SIZE); in TEST() local
266 EXPECT_MEM_EQ(src3, dst3); in TEST()
406 MemoryView src3(data, sizeof(data)), in TEST() local
408 EXPECT_MEM_EQ(src3, dst3); in TEST()
/llvm-project-15.0.7/lldb/test/API/tools/lldb-vscode/step/
H A DTestVSCode_step.py61 (src3, line3) = self.get_source_and_line(threadId=tid)
64 self.assertEqual(src1, src3, 'verify step in source')
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dbranch-hint.ll105 define void @branch_hint_6(i32 %src1, i32 %src2, i32 %src3) {
119 %cmp4 = icmp eq i32 %src3, 1
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZOperators.td657 def z_muladd : PatFrag<(ops node:$src1, node:$src2, node:$src3),
658 (add (mul node:$src1, node:$src2), node:$src3)>;
687 def any_fms : PatFrag<(ops node:$src1, node:$src2, node:$src3),
688 (any_fma node:$src1, node:$src2, (fneg node:$src3))>;
692 def z_any_fma : PatFrag<(ops node:$src1, node:$src2, node:$src3),
693 (any_fma node:$src2, node:$src3, node:$src1)>;
694 def z_any_fms : PatFrag<(ops node:$src1, node:$src2, node:$src3),
698 def any_fnma : PatFrag<(ops node:$src1, node:$src2, node:$src3),
699 (fneg (any_fma node:$src1, node:$src2, node:$src3))>;
700 def any_fnms : PatFrag<(ops node:$src1, node:$src2, node:$src3),
[all …]

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