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/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dpeephole-phi.mir23 ; CHECK: [[DEF1:%[0-9]+]]:spr = IMPLICIT_DEF
37 %3:spr = IMPLICIT_DEF
38 %4:gpr = VMOVRS %3:spr, 14, $noreg
42 %6:spr = VMOVSR %5, 14, $noreg
70 %1:spr = IMPLICIT_DEF
75 %3:spr = IMPLICIT_DEF
76 %2:gpr = VMOVRS %3:spr, 14, $noreg
80 %5:spr = VMOVSR %4, 14, $noreg
108 %0:gpr = VMOVRS undef %1:spr, 14, $noreg
112 %2:gpr = VMOVRS undef %3:spr, 14, $noreg
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dswp-fixedii.mir115 ; CHECK-NEXT: [[PHI3:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.6, %43, %bb.7
116 ; CHECK-NEXT: [[PHI4:%[0-9]+]]:spr = PHI [[VMULS1]], %bb.6, %52, %bb.7
117 ; CHECK-NEXT: [[PHI5:%[0-9]+]]:spr = PHI [[VMULS]], %bb.6, [[PHI4]], %bb.7
134 ; CHECK-NEXT: [[PHI6:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.6, [[VADDS]], %bb.7
135 ; CHECK-NEXT: [[PHI7:%[0-9]+]]:spr = PHI [[VMULS1]], %bb.6, [[VMULS2]], %bb.7
136 ; CHECK-NEXT: [[PHI8:%[0-9]+]]:spr = PHI [[VMULS]], %bb.6, [[PHI4]], %bb.7
142 ; CHECK-NEXT: [[PHI9:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.5, [[VADDS1]], %bb.8
143 ; CHECK-NEXT: [[PHI10:%[0-9]+]]:spr = PHI [[VMULS]], %bb.5, [[PHI7]], %bb.8
148 ; CHECK-NEXT: [[PHI11:%[0-9]+]]:spr = PHI [[VLDRS]], %bb.1, [[VADDS2]], %bb.9
183 %5:spr = PHI %15, %bb.1, %6, %bb.2
[all …]
H A Dswp-exitbranchdir.mir115 ; CHECK-NEXT: [[PHI3:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.6, %43, %bb.7
116 ; CHECK-NEXT: [[PHI4:%[0-9]+]]:spr = PHI [[VMULS1]], %bb.6, %52, %bb.7
117 ; CHECK-NEXT: [[PHI5:%[0-9]+]]:spr = PHI [[VMULS]], %bb.6, [[PHI4]], %bb.7
134 ; CHECK-NEXT: [[PHI6:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.6, [[VADDS]], %bb.7
135 ; CHECK-NEXT: [[PHI7:%[0-9]+]]:spr = PHI [[VMULS1]], %bb.6, [[VMULS2]], %bb.7
136 ; CHECK-NEXT: [[PHI8:%[0-9]+]]:spr = PHI [[VMULS]], %bb.6, [[PHI4]], %bb.7
142 ; CHECK-NEXT: [[PHI9:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.5, [[VADDS1]], %bb.8
143 ; CHECK-NEXT: [[PHI10:%[0-9]+]]:spr = PHI [[VMULS]], %bb.5, [[PHI7]], %bb.8
148 ; CHECK-NEXT: [[PHI11:%[0-9]+]]:spr = PHI [[VLDRS]], %bb.1, [[VADDS2]], %bb.9
183 %5:spr = PHI %15, %bb.1, %6, %bb.2
[all …]
H A Dswp-fixedii-le.mir103 ; CHECK-NEXT: [[PHI3:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.5, %46, %bb.6
104 ; CHECK-NEXT: [[PHI4:%[0-9]+]]:spr = PHI [[VMULS]], %bb.5, %45, %bb.6
122 ; CHECK-NEXT: [[PHI5:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.5, [[VADDS]], %bb.6
123 ; CHECK-NEXT: [[PHI6:%[0-9]+]]:spr = PHI [[VMULS]], %bb.5, [[VMULS1]], %bb.6
128 ; CHECK-NEXT: [[PHI7:%[0-9]+]]:spr = PHI [[VLDRS]], %bb.1, [[VADDS1]], %bb.7
145 %14:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool)
154 %15:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool)
164 %5:spr = PHI %15, %bb.1, %6, %bb.2
166 %19:spr = VLDRS %2, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7)
168 %21:spr = VLDRS %3, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/GlobalISel/
H A Dselect-fp.mir93 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
96 ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1
153 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
156 ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1
213 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
216 ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1
273 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
276 ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1
332 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
387 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
[all …]
H A Darm-instruction-select-combos.mir448 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
449 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
478 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
479 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
539 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
540 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
541 ; CHECK: [[COPY2:%[0-9]+]]:spr = COPY $s2
607 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
608 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
609 ; CHECK: [[COPY2:%[0-9]+]]:spr = COPY $s2
[all …]
H A Darm-instruction-select-cmp.mir422 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
453 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
484 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
515 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
546 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
577 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
608 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
639 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
670 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
701 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
[all …]
H A Darm-select-copy_to_regclass-of-fptosi.mir21 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
22 ; CHECK: [[VTOSIZS:%[0-9]+]]:spr = VTOSIZS [[COPY]], 14 /* CC::al */, $noreg
H A Dselect-fp-const.mir35 …; CHECK: [[VREG:%[0-9]+]]:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from con…
98 ; VFP3: [[VREG:%[0-9]+]]:spr = FCONSTS 128, 14 /* CC::al */, $noreg
99 …; VFP2: [[VREG:%[0-9]+]]:spr = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from cons…
H A Dselect-dbg.mir41 ; DBG_VALUE {{%[0-9]+}}:spr, $noreg, !7, !DIExpression(), debug-location !9
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dvec_vrsave.ll8 ; CHECK-NOT: spr
17 ; CHECK-NOT: spr
/llvm-project-15.0.7/mlir/test/Integration/Dialect/Vector/CPU/AMX/
H A Dlit.local.cfg13 config.substitutions.append(('%lli', config.intel_sde_executable + ' -spr -- lli'))
/llvm-project-15.0.7/lldb/source/Plugins/Instruction/PPC64/
H A DEmulateInstructionPPC64.cpp205 uint32_t spr = Bits32(opcode, 20, 11); in EmulateMFSPR() local
210 if (rt != gpr_r0_ppc64le || spr != SPR_LR) in EmulateMFSPR()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td1610 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
1613 let SPR = spr;
1672 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
1675 let SPR = spr;