1 //===- HexagonMCInstrInfo.cpp - Utility functions on Hexagon MCInsts ------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Utility functions for Hexagon specific MCInst queries
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H
14 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H
15 
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/iterator_range.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/Support/MathExtras.h"
21 #include <cstddef>
22 #include <cstdint>
23 
24 namespace llvm {
25 
26 class HexagonMCChecker;
27 class MCContext;
28 class MCExpr;
29 class MCInstrDesc;
30 class MCInstrInfo;
31 class MCRegisterInfo;
32 class MCSubtargetInfo;
33 
34 class DuplexCandidate {
35 public:
36   unsigned packetIndexI, packetIndexJ, iClass;
37 
DuplexCandidate(unsigned i,unsigned j,unsigned iClass)38   DuplexCandidate(unsigned i, unsigned j, unsigned iClass)
39       : packetIndexI(i), packetIndexJ(j), iClass(iClass) {}
40 };
41 
42 namespace Hexagon {
43 
44 class PacketIterator : public std::iterator<std::forward_iterator_tag,
45     PacketIterator> {
46   MCInstrInfo const &MCII;
47   MCInst::const_iterator BundleCurrent;
48   MCInst::const_iterator BundleEnd;
49   MCInst::const_iterator DuplexCurrent;
50   MCInst::const_iterator DuplexEnd;
51 
52 public:
53   PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst);
54   PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst, std::nullptr_t);
55 
56   PacketIterator &operator++();
57   MCInst const &operator*() const;
58   bool operator==(PacketIterator const &Other) const;
59   bool operator!=(PacketIterator const &Other) const {
60     return !(*this == Other);
61   }
62 };
63 
64 } // end namespace Hexagon
65 
66 namespace HexagonMCInstrInfo {
67 
68 constexpr size_t innerLoopOffset = 0;
69 constexpr int64_t innerLoopMask = 1 << innerLoopOffset;
70 
71 constexpr size_t outerLoopOffset = 1;
72 constexpr int64_t outerLoopMask = 1 << outerLoopOffset;
73 
74 // do not reorder memory load/stores by default load/stores are re-ordered
75 // and by default loads can be re-ordered
76 constexpr size_t memReorderDisabledOffset = 2;
77 constexpr int64_t memReorderDisabledMask = 1 << memReorderDisabledOffset;
78 
79 constexpr size_t splitNoMemOrderOffset = 3;
80 constexpr int64_t splitNoMemorderMask = 1 << splitNoMemOrderOffset;
81 
82 constexpr size_t noShuffleOffset = 4;
83 constexpr int64_t noShuffleMask = 1 << noShuffleOffset;
84 
85 constexpr size_t bundleInstructionsOffset = 1;
86 
87 void addConstant(MCInst &MI, uint64_t Value, MCContext &Context);
88 void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
89                       MCInst const &MCI);
90 
91 // Returns a iterator range of instructions in this bundle
92 iterator_range<Hexagon::PacketIterator>
93 bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI);
94 iterator_range<MCInst::const_iterator> bundleInstructions(MCInst const &MCI);
95 
96 // Returns the number of instructions in the bundle
97 size_t bundleSize(MCInst const &MCI);
98 
99 // Put the packet in to canonical form, compound, duplex, pad, and shuffle
100 bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
101                         MCContext &Context, MCInst &MCB,
102                         HexagonMCChecker *Checker,
103                         bool AttemptCompatibility = false);
104 bool IsABranchingInst(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
105                       MCInst const &I);
106 
107 // Create a duplex instruction given the two subinsts
108 MCInst *deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0,
109                      MCInst const &inst1);
110 MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst,
111                       MCOperand const &MO);
112 
113 // Convert this instruction in to a duplex subinst
114 MCInst deriveSubInst(MCInst const &Inst);
115 
116 // Return the extender for instruction at Index or nullptr if none
117 MCInst const *extenderForIndex(MCInst const &MCB, size_t Index);
118 void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
119                     MCInst const &MCI);
120 
121 // Return memory access size in bytes
122 unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI);
123 
124 // Return memory access size
125 unsigned getAddrMode(MCInstrInfo const &MCII, MCInst const &MCI);
126 
127 MCInstrDesc const &getDesc(MCInstrInfo const &MCII, MCInst const &MCI);
128 
129 // Return which duplex group this instruction belongs to
130 unsigned getDuplexCandidateGroup(MCInst const &MI);
131 
132 // Return a list of all possible instruction duplex combinations
133 SmallVector<DuplexCandidate, 8>
134 getDuplexPossibilties(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
135                       MCInst const &MCB);
136 unsigned getDuplexRegisterNumbering(unsigned Reg);
137 
138 MCExpr const &getExpr(MCExpr const &Expr);
139 
140 // Return the index of the extendable operand
141 unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI);
142 
143 // Return a reference to the extendable operand
144 MCOperand const &getExtendableOperand(MCInstrInfo const &MCII,
145                                       MCInst const &MCI);
146 
147 // Return the implicit alignment of the extendable operand
148 unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI);
149 
150 // Return the number of logical bits of the extendable operand
151 unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI);
152 
153 // Check if the extendable operand is signed.
154 bool isExtentSigned(MCInstrInfo const &MCII, MCInst const &MCI);
155 
156 // Return the max value that a constant extendable operand can have
157 // without being extended.
158 int getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI);
159 
160 // Return the min value that a constant extendable operand can have
161 // without being extended.
162 int getMinValue(MCInstrInfo const &MCII, MCInst const &MCI);
163 
164 // Return instruction name
165 StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI);
166 
167 // Return the operand index for the new value.
168 unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI);
169 
170 // Return the operand that consumes or produces a new value.
171 MCOperand const &getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI);
172 unsigned short getNewValueOp2(MCInstrInfo const &MCII, MCInst const &MCI);
173 MCOperand const &getNewValueOperand2(MCInstrInfo const &MCII,
174                                      MCInst const &MCI);
175 
176 // Return the Hexagon ISA class for the insn.
177 unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI);
178 
179 /// Return the resources used by this instruction
180 unsigned getCVIResources(MCInstrInfo const &MCII,
181                                       MCSubtargetInfo const &STI,
182                                       MCInst const &MCI);
183 
184 /// Return the slots used by the insn.
185 unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
186                   MCInst const &MCI);
187 unsigned getOtherReservedSlots(MCInstrInfo const &MCII,
188                                MCSubtargetInfo const &STI, MCInst const &MCI);
189 bool hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI);
190 
191 // Does the packet have an extender for the instruction at Index
192 bool hasExtenderForIndex(MCInst const &MCB, size_t Index);
193 
194 bool hasImmExt(MCInst const &MCI);
195 
196 // Return whether the instruction is a legal new-value producer.
197 bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI);
198 bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI);
199 bool hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI);
200 bool hasHvxTmp(MCInstrInfo const &MCII, MCInst const &MCI);
201 unsigned iClassOfDuplexPair(unsigned Ga, unsigned Gb);
202 
203 int64_t minConstant(MCInst const &MCI, size_t Index);
204 template <unsigned N, unsigned S>
inRange(MCInst const & MCI,size_t Index)205 bool inRange(MCInst const &MCI, size_t Index) {
206   return isShiftedUInt<N, S>(minConstant(MCI, Index));
207 }
208 template <unsigned N, unsigned S>
inSRange(MCInst const & MCI,size_t Index)209 bool inSRange(MCInst const &MCI, size_t Index) {
210   return isShiftedInt<N, S>(minConstant(MCI, Index));
211 }
inRange(MCInst const & MCI,size_t Index)212 template <unsigned N> bool inRange(MCInst const &MCI, size_t Index) {
213   return isUInt<N>(minConstant(MCI, Index));
214 }
215 
216 // Return the instruction at Index
217 MCInst const &instruction(MCInst const &MCB, size_t Index);
218 bool isAccumulator(MCInstrInfo const &MCII, MCInst const &MCI);
219 
220 // Returns whether this MCInst is a wellformed bundle
221 bool isBundle(MCInst const &MCI);
222 
223 // Return whether the insn is an actual insn.
224 bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI);
225 bool isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI);
226 bool isCofRelax1(MCInstrInfo const &MCII, MCInst const &MCI);
227 bool isCofRelax2(MCInstrInfo const &MCII, MCInst const &MCI);
228 bool isCompound(MCInstrInfo const &MCII, MCInst const &MCI);
229 
230 // Return whether the instruction needs to be constant extended.
231 bool isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI);
232 bool isCVINew(MCInstrInfo const &MCII, MCInst const &MCI);
233 
234 // Is this double register suitable for use in a duplex subinst
235 bool isDblRegForSubInst(unsigned Reg);
236 
237 // Is this a duplex instruction
238 bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI);
239 
240 // Can these instructions be duplexed
241 bool isDuplexPair(MCInst const &MIa, MCInst const &MIb);
242 
243 // Can these duplex classes be combine in to a duplex instruction
244 bool isDuplexPairMatch(unsigned Ga, unsigned Gb);
245 
246 // Return true if the insn may be extended based on the operand value.
247 bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI);
248 
249 // Return whether the instruction must be always extended.
250 bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI);
251 
252 /// Return whether it is a floating-point insn.
253 bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI);
254 
255 bool isHVX(MCInstrInfo const &MCII, MCInst const &MCI);
256 
257 // Returns whether this instruction is an immediate extender
258 bool isImmext(MCInst const &MCI);
259 
260 // Returns whether this bundle is an endloop0
261 bool isInnerLoop(MCInst const &MCI);
262 
263 // Is this an integer register
264 bool isIntReg(unsigned Reg);
265 
266 // Is this register suitable for use in a duplex subinst
267 bool isIntRegForSubInst(unsigned Reg);
268 bool isMemReorderDisabled(MCInst const &MCI);
269 
270 // Return whether the insn is a new-value consumer.
271 bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI);
272 /// Return true if the operand is a new-value store insn.
273 bool isNewValueStore(MCInstrInfo const &MCII, MCInst const &MCI);
274 bool isOpExtendable(MCInstrInfo const &MCII, MCInst const &MCI, unsigned short);
275 
276 // Can these two instructions be duplexed
277 bool isOrderedDuplexPair(MCInstrInfo const &MCII, MCInst const &MIa,
278                          bool ExtendedA, MCInst const &MIb, bool ExtendedB,
279                          bool bisReversable, MCSubtargetInfo const &STI);
280 
281 // Returns whether this bundle is an endloop1
282 bool isOuterLoop(MCInst const &MCI);
283 
284 // Return whether this instruction is predicated
285 bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI);
286 bool isPredicateLate(MCInstrInfo const &MCII, MCInst const &MCI);
287 bool isPredicatedNew(MCInstrInfo const &MCII, MCInst const &MCI);
288 
289 // Return whether the predicate sense is true
290 bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI);
291 
292 // Return true if this is a scalar predicate register.
293 bool isPredReg(MCRegisterInfo const &MRI, unsigned Reg);
294 
295 // Returns true if the Ith operand is a predicate register.
296 bool isPredRegister(MCInstrInfo const &MCII, MCInst const &Inst, unsigned I);
297 
298 // Return whether the insn is a prefix.
299 bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI);
300 
301 // Return whether the insn is solo, i.e., cannot be in a packet.
302 bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI);
303 
304 /// Return whether the insn can be packaged only with A and X-type insns.
305 bool isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI);
306 
307 /// Return whether the insn can be packaged only with an A-type insn in slot #1.
308 bool isRestrictSlot1AOK(MCInstrInfo const &MCII, MCInst const &MCI);
309 bool isRestrictNoSlot1Store(MCInstrInfo const &MCII, MCInst const &MCI);
310 bool isSubInstruction(MCInst const &MCI);
311 bool isVector(MCInstrInfo const &MCII, MCInst const &MCI);
312 bool mustExtend(MCExpr const &Expr);
313 bool mustNotExtend(MCExpr const &Expr);
314 
315 // Returns true if this instruction requires a slot to execute.
316 bool requiresSlot(MCSubtargetInfo const &STI, MCInst const &MCI);
317 
318 
319 // Returns true if \a MCB would require endloop padding.
320 bool LoopNeedsPadding(MCInst const &MCB);
321 
322 unsigned packetSize(StringRef CPU);
323 
324 // Returns the maximum number of slots available in the given
325 // subtarget's packets.
326 unsigned packetSizeSlots(MCSubtargetInfo const &STI);
327 
328 // Returns the number of slots consumed by this packet, considering duplexed
329 // and compound instructions.
330 unsigned slotsConsumed(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
331                        MCInst const &MCI);
332 
333 // Pad the bundle with nops to satisfy endloop requirements.
334 void padEndloop(MCInst &MCI, MCContext &Context);
335 class PredicateInfo {
336 public:
PredicateInfo()337   PredicateInfo() : Register(0), Operand(0), PredicatedTrue(false) {}
PredicateInfo(unsigned Register,unsigned Operand,bool PredicatedTrue)338   PredicateInfo(unsigned Register, unsigned Operand, bool PredicatedTrue)
339       : Register(Register), Operand(Operand), PredicatedTrue(PredicatedTrue) {}
340   bool isPredicated() const;
341   unsigned Register;
342   unsigned Operand;
343   bool PredicatedTrue;
344 };
345 PredicateInfo predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI);
346 bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI);
347 
348 // Replace the instructions inside MCB, represented by Candidate
349 void replaceDuplex(MCContext &Context, MCInst &MCI, DuplexCandidate Candidate);
350 
351 bool s27_2_reloc(MCExpr const &Expr);
352 // Marks a bundle as endloop0
353 void setInnerLoop(MCInst &MCI);
354 void setMemReorderDisabled(MCInst &MCI);
355 void setMustExtend(MCExpr const &Expr, bool Val = true);
356 void setMustNotExtend(MCExpr const &Expr, bool Val = true);
357 void setS27_2_reloc(MCExpr const &Expr, bool Val = true);
358 
359 // Marks a bundle as endloop1
360 void setOuterLoop(MCInst &MCI);
361 
362 // Would duplexing this instruction create a requirement to extend
363 bool subInstWouldBeExtended(MCInst const &potentialDuplex);
364 unsigned SubregisterBit(unsigned Consumer, unsigned Producer,
365                         unsigned Producer2);
366 
367 bool IsVecRegSingle(unsigned VecReg);
368 bool IsVecRegPair(unsigned VecReg);
369 bool IsReverseVecRegPair(unsigned VecReg);
370 bool IsSingleConsumerRefPairProducer(unsigned Producer, unsigned Consumer);
371 
372 /// Returns an ordered pair of the constituent register ordinals for
373 /// each of the elements of \a VecRegPair.  For example, Hexagon::W0 ("v0:1")
374 /// returns { 0, 1 } and Hexagon::W1 ("v3:2") returns { 3, 2 }.
375 std::pair<unsigned, unsigned> GetVecRegPairIndices(unsigned VecRegPair);
376 
377 // Attempt to find and replace compound pairs
378 void tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
379                  MCContext &Context, MCInst &MCI);
380 
381 } // end namespace HexagonMCInstrInfo
382 
383 } // end namespace llvm
384 
385 #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H
386