| /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| H A D | regbankselect-dyn-stackalloc.mir | 25 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
34 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
59 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
68 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
93 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
102 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
127 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
136 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
161 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
170 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
[all …]
|
| H A D | irtranslator-call-sret.ll | 53 ; GCN-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg
|
| H A D | irtranslator-call.ll | 2543 ; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg
2639 ; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg
2735 ; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg
3546 ; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg
3644 ; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg
3747 ; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg
3860 ; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg
4084 ; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg
4664 ; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg
|
| H A D | irtranslator-call-implicit-args.ll | 247 ; GFX900-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg
335 ; GFX908-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg
|
| /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/ |
| H A D | remat-dead-subreg.mir | 16 …LL_S32_SAVE killed renamable $sgpr1, %stack.0, implicit $exec, implicit $sp_reg :: (store (s32) in…
20 …; GCN-NEXT: renamable $sgpr1 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sp_reg :: …
41 …LL_S32_SAVE killed renamable $sgpr2, %stack.0, implicit $exec, implicit $sp_reg :: (store (s32) in…
43 …; GCN-NEXT: renamable $sgpr0 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sp_reg :: …
66 …_SAVE killed renamable $sgpr4_sgpr5, %stack.0, implicit $exec, implicit $sp_reg :: (store (s64) in…
70 … $sgpr4_sgpr5 = SI_SPILL_S64_RESTORE %stack.0, implicit $exec, implicit $sp_reg :: (load (s64) fro…
|
| H A D | splitkit-nolivesubranges.mir | 28 …ILL_S64_SAVE renamable $sgpr0_sgpr1, %stack.0, implicit $exec, implicit $sp_reg :: (store (s64) in…
30 … $sgpr0_sgpr1 = SI_SPILL_S64_RESTORE %stack.0, implicit $exec, implicit $sp_reg :: (load (s64) fro…
|
| /llvm-project-15.0.7/lldb/source/Plugins/ABI/Hexagon/ |
| H A D | ABISysV_hexagon.cpp | 990 uint32_t sp_reg = reg_ctx->ConvertRegisterKindToRegisterNumber( in PrepareTrivialCall() local
992 if (sp_reg == LLDB_INVALID_REGNUM) in PrepareTrivialCall()
1069 reg_ctx->WriteRegisterFromUnsigned(sp_reg, sp); in PrepareTrivialCall()
|
| /llvm-project-15.0.7/lldb/source/Plugins/ABI/ARC/ |
| H A D | ABISysV_arc.cpp | 213 uint32_t sp_reg = reg_ctx->ConvertRegisterKindToRegisterNumber( in PrepareTrivialCall() local
215 if (sp_reg == LLDB_INVALID_REGNUM) in PrepareTrivialCall()
302 reg_ctx->WriteRegisterFromUnsigned(sp_reg, sp); in PrepareTrivialCall()
|
| /llvm-project-15.0.7/llvm/test/CodeGen/MIR/AMDGPU/ |
| H A D | machine-function-info-no-ir.mir | 121 # FULL-NEXT: stackPtrOffsetReg: '$sp_reg'
190 # FULL-NEXT: stackPtrOffsetReg: '$sp_reg'
260 # FULL-NEXT: stackPtrOffsetReg: '$sp_reg'
321 # FULL-NEXT: stackPtrOffsetReg: '$sp_reg'
|
| /llvm-project-15.0.7/lldb/source/Plugins/Instruction/ARM/ |
| H A D | EmulateInstructionARM.cpp | 973 RegisterInfo sp_reg; in EmulatePUSH() local
1100 RegisterInfo sp_reg; in EmulatePOP() local
1187 RegisterInfo sp_reg; in EmulateADDRdSPImm() local
1243 RegisterInfo sp_reg; in EmulateMOVRdSP() local
1245 context.SetRegisterPlusOffset(sp_reg, 0); in EmulateMOVRdSP()
1911 RegisterInfo sp_reg; in EmulateADDSPImm() local
1978 RegisterInfo sp_reg; in EmulateADDSPRm() local
2516 RegisterInfo sp_reg; in EmulateSTRRtSP() local
2616 RegisterInfo sp_reg; in EmulateVPUSH() local
2709 RegisterInfo sp_reg; in EmulateVPOP() local
[all …]
|
| /llvm-project-15.0.7/llvm/test/CodeGen/AVR/inline-asm/ |
| H A D | inline-asm.ll | 58 ; define void @sp_reg(i16 %var)
|