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/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dinc-of-add.ll2 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse,+sse2,+slow-lea,+slow-3ops-lea | FileCh…
3 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse,+sse2,-slow-lea,-slow-3ops-lea | FileCh…
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse,+sse2,+slow-lea,+slow-3ops-lea | FileCh…
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse,+sse2,-slow-lea,-slow-3ops-lea | FileCh…
H A Dsub-of-not.ll2 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse,+sse2,+slow-lea,+slow-3ops-lea | FileCh…
3 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse,+sse2,-slow-lea,-slow-3ops-lea | FileCh…
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse,+sse2,+slow-lea,+slow-3ops-lea | FileCh…
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse,+sse2,-slow-lea,-slow-3ops-lea | FileCh…
H A Dneg-of-3ops-lea.ll2 ; RUN: llc < %s -mtriple=i686-- -mattr=+slow-3ops-lea | FileCheck %s --check-prefix=X86
3 ; RUN: llc < %s -mtriple=i686-- -mattr=-slow-3ops-lea | FileCheck %s --check-prefix=X86
4 ; RUN: llc < %s -mtriple=x86_64-- -mattr=+slow-3ops-lea | FileCheck %s --check-prefix=X64
5 ; RUN: llc < %s -mtriple=x86_64-- -mattr=-slow-3ops-lea | FileCheck %s --check-prefix=X64
H A Dbitcast-i256.ll2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,-slow-unaligned-mem-32 | FileCheck %s -…
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+slow-unaligned-mem-32 | FileCheck %s -…
H A Dslow-unaligned-mem.ll1 ; Intel chips with slow unaligned memory accesses
27 ; AMD chips with slow unaligned memory accesses
53 ; Other chips with slow unaligned memory accesses
57 ; Verify that the slow/fast unaligned memory attribute is set correctly for each CPU model.
H A Ddag-merge-fast-accesses.ll2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-slow-unaligned-mem-16 | FileCheck %s --chec…
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+slow-unaligned-mem-16 | FileCheck %s --chec…
H A Dvec_loadsingles.ll2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,-slow-unaligned-mem-32 | FileCheck %s -…
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+slow-unaligned-mem-32 | FileCheck %s -…
58 ; If the target has slow 32-byte accesses, we should still generate
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsdag-store-merging-bug.ll2 ; RUN: llc -o - %s -mtriple aarch64-- -mattr +slow-misaligned-128store | FileCheck %s
7 ; via the aarch64 slow-misaligned-128store code splitting stores earlier.
9 ; aarch64 feature slow-misaligned-128store splits the following store.
H A Dmerge-store.ll2 ; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mcpu=cyclone -mattr=+slow-misaligned-128store | F…
3 ; RUN: llc < %s -mtriple=aarch64-eabi -mattr=-slow-misaligned-128store | FileCheck %s --check-prefi…
41 ; unaligned 16-byte stores are slow. This test would infinite loop when
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dinfinite-loop-postdom.ll155 ; CHECK-POSTDOM-NEXT: Inorder PostDominator Tree: DFSNumbers invalid: 0 slow queries.
165 ; CHECK-POSTDOM-NEXT: Inorder PostDominator Tree: DFSNumbers invalid: 0 slow queries.
175 ; CHECK-POSTDOM-NEXT: Inorder PostDominator Tree: DFSNumbers invalid: 0 slow queries.
185 ; CHECK-POSTDOM-NEXT: Inorder PostDominator Tree: DFSNumbers invalid: 0 slow queries.
195 ; CHECK-POSTDOM-NEXT:Inorder PostDominator Tree: DFSNumbers invalid: 0 slow queries.
210 ; CHECK-POSTDOM-NEXT:Inorder PostDominator Tree: DFSNumbers invalid: 0 slow queries.
/llvm-project-15.0.7/clang/test/Driver/
H A Dcl-denorms-are-zero.cl1 // Slow FMAF and slow f32 denormals
5 // Fast FMAF, but slow f32 denormals
9 // Fast F32 denormals, but slow FMAF
/llvm-project-15.0.7/lld/test/MachO/
H A Dcompact-unwind-generated.test3 # FIXME(gkm): This test is fast on a Release tree, and slow (~10s) on
5 # fast installed llvm-mc rather than the slow one in our Debug tree?
/llvm-project-15.0.7/llvm/test/Transforms/CodeGenPrepare/NVPTX/
H A Dbypass-slow-div-constant-numerator.ll6 ; When we bypass slow div with a constant numerator which fits into the bypass
20 ; When we try to bypass slow div with a constant numerator which *doesn't* fit
/llvm-project-15.0.7/polly/test/ScopInfo/
H A Dwraping_signed_expr_slow_2.ll17 ; void slow(char *A, char N, char M) {
27 ; CHECK: Function: slow
59 define void @slow(i8* %A, i8 %N, i8 %M) {
H A Dwraping_signed_expr_slow_1.ll21 ; CHECK: Function: slow
54 define void @slow(i8* %A, i8 %N, i8 %M) {
/llvm-project-15.0.7/llvm/lib/Support/
H A Dregengine.inc48 #define slow sslow
61 #define slow lslow
201 endp = slow(m, m->coldp, stop, gf, gl);
388 rest = slow(m, sp, stp, ss, es);
391 tail = slow(m, rest, stop, es, stopst);
413 rest = slow(m, sp, stp, ss, es);
416 tail = slow(m, rest, stop, es, stopst);
428 sep = slow(m, ssp, rest, ssub, esub);
452 rest = slow(m, sp, stp, ss, es);
815 AT("slow", start, stop, startst, stopst);
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/X86/
H A Davx1.ll1 ; RUN: opt < %s -loop-vectorize -mattr=avx,+slow-unaligned-mem-32 -S | FileCheck %s --check-prefix…
2 ; RUN: opt < %s -loop-vectorize -mattr=avx,-slow-unaligned-mem-32 -S | FileCheck %s --check-prefix…
/llvm-project-15.0.7/compiler-rt/lib/xray/
H A Dxray_trampoline_powerpc64_asm.S9 # If this appears to be slow, the caller needs to pass in number of generic,
150 # If this appears to be slow, the caller needs to pass in number of generic,
/llvm-project-15.0.7/llvm/test/Assembler/
H A D2002-10-08-LargeArrayPerformance.ll5 ;;; We should not be soo slow for such a simple case!
/llvm-project-15.0.7/clang-tools-extra/docs/clang-tidy/checks/bugprone/
H A Dincorrect-roundings.rst13 1. It is unnecessarily slow.
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86.td402 def TuningSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
403 "SHLD instruction is slow">;
405 def TuningSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",
408 def TuningSlowPMADDWD : SubtargetFeature<"slow-pmaddwd", "IsPMADDWDSlow",
413 def TuningSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
417 def TuningSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
441 // slow. In practice, this means that CALL, PUSH, and POP with memory operands
443 def TuningSlowTwoMemOps : SubtargetFeature<"slow-two-mem-ops",
452 def TuningSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
461 // True if INC and DEC instructions are slow when writing to flags
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/Vector/
H A Dvector-transfer-full-partial-split.mlir45 // slow path, fill tmp alloc and yield a memref_casted version of it
46 // CHECK: %[[slow:.*]] = vector.transfer_read %[[A]][%[[i]], %[[j]]], %cst :
50 // CHECK: store %[[slow]], %[[cast_alloc]][] : memref<vector<4x8xf32>>
77 // slow path, fill tmp alloc and yield a memref_casted version of it
134 // slow path, fill tmp alloc and yield a memref_casted version of it
135 // CHECK: %[[slow:.*]] = vector.transfer_read %[[A]][%[[i]], %[[j]]], %cst :
139 // CHECK: store %[[slow]], %[[cast_alloc]][] :
170 // slow path, fill tmp alloc and yield a memref_casted version of it
/llvm-project-15.0.7/flang/unittests/
H A DCMakeLists.txt20 set(suffix .slow)
/llvm-project-15.0.7/lldb/examples/synthetic/
H A Dlibcxx.py252 slow = stdlist_entry(self.head)
255 while slow.next.value != self.node_address:
256 slow_value = slow.value
261 slow = slow.next
H A Dgnu_libstdcpp.py175 slow = self.next
178 while self.is_valid(slow):
179 slow_value = self.value(slow)
185 slow = self.next_node(slow)

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