Home
last modified time | relevance | path

Searched refs:sll (Results 1 – 25 of 281) sorted by relevance

12345678910>>...12

/llvm-project-15.0.7/clang/test/CodeGen/
H A DAtomics.c11 signed long long sll; variable
84 sll = __sync_fetch_and_add (&sll, 11); // CHECK: atomicrmw add in test_fetch_and_op()
93 sll = __sync_fetch_and_sub (&sll, 11); // CHECK: atomicrmw sub in test_fetch_and_op()
102 sll = __sync_fetch_and_or (&sll, 11); // CHECK: atomicrmw or in test_fetch_and_op()
111 sll = __sync_fetch_and_xor (&sll, 11); // CHECK: atomicrmw xor in test_fetch_and_op()
129 sll = __sync_fetch_and_and (&sll, 11); // CHECK: atomicrmw and in test_fetch_and_op()
142 sll = __sync_add_and_fetch (&sll, uc); // CHECK: atomicrmw add in test_op_and_fetch()
151 sll = __sync_sub_and_fetch (&sll, uc); // CHECK: atomicrmw sub in test_op_and_fetch()
160 sll = __sync_or_and_fetch (&sll, uc); // CHECK: atomicrmw or in test_op_and_fetch()
169 sll = __sync_xor_and_fetch (&sll, uc); // CHECK: atomicrmw xor in test_op_and_fetch()
[all …]
H A Dcomplex-convert.c138 csc1 = sll; in foo()
168 cuc1 = sll; in foo()
200 csll1 = sll; in foo()
230 cull1 = sll; in foo()
372 csll1 = sll + csc; in foo()
387 csll1 = sll + cuc; in foo()
402 csll1 = sll + csll; in foo()
415 csll1 = sll + cull; in foo()
520 csll1 = csc + sll; in foo()
586 csll1 = cuc + sll; in foo()
[all …]
H A Dbuiltins-nvptx.c209 __shared__ long long sll; variable
221 __nvvm_atom_add_gen_ll(&sll, ll); in nvvm_atom()
228 __nvvm_atom_sub_gen_ll(&sll, ll); in nvvm_atom()
235 __nvvm_atom_and_gen_ll(&sll, ll); in nvvm_atom()
242 __nvvm_atom_or_gen_ll(&sll, ll); in nvvm_atom()
249 __nvvm_atom_xor_gen_ll(&sll, ll); in nvvm_atom()
256 __nvvm_atom_xchg_gen_ll(&sll, ll); in nvvm_atom()
267 __nvvm_atom_max_gen_ll(&sll, ll); in nvvm_atom()
280 __nvvm_atom_min_gen_ll(&sll, ll); in nvvm_atom()
292 __nvvm_atom_cas_gen_ll(&sll, 0, ll); in nvvm_atom()
[all …]
H A DNontemporal.cpp10 signed long long sll; variable
29 __builtin_nontemporal_store(1, &sll); // CHECK: store i64{{.*}}align 8, !nontemporal in test_all_sizes()
42 ull = __builtin_nontemporal_load(&sll); // CHECK: load i64{{.*}}align 8, !nontemporal in test_all_sizes()
43 sll = __builtin_nontemporal_load(&ull); // CHECK: load i64{{.*}}align 8, !nontemporal in test_all_sizes()
/llvm-project-15.0.7/clang/test/CodeGen/PowerPC/
H A Dbuiltins-ppc-xlcompat-pwr9-64bit.c13 extern signed long long sll;
21 return __builtin_ppc_cmpeqb(sll, sll); in test_builtin_ppc_cmpeqb()
29 return __builtin_ppc_setb(sll, sll); in test_builtin_ppc_setb()
37 return __builtin_ppc_maddhd(sll, sll, sll); in test_builtin_ppc_maddhd()
53 return __builtin_ppc_maddld(sll, sll, sll); in test_builtin_ppc_maddld()
89 return __builtin_ppc_addex(sll, sll, 0); in test_builtin_ppc_addex0()
/llvm-project-15.0.7/llvm/test/MC/VE/
H A DSLL.s6 # CHECK-INST: sll %s11, %s11, %s11
8 sll %s11, %s11, %s11 label
10 # CHECK-INST: sll %s11, %s11, 63
12 sll %s11, %s11, 63 label
14 # CHECK-INST: sll %s11, %s11, 127
16 sll %s11, %s11, 127 label
18 # CHECK-INST: sll %s11, %s11, 64
20 sll %s11, %s11, 64 label
22 # CHECK-INST: sll %s11, (32)1, 35
24 sll %s11, (32)1, 35 label
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A DAtomics.ll4 @sll = common global i64 0, align 8
9 %t01 = atomicrmw add i64* @sll, i64 1 monotonic
13 %t21 = atomicrmw or i64* @sll, i64 1 monotonic
31 store i64 %t01, i64* @sll, align 8
35 store i64 %t11, i64* @sll, align 8
39 store i64 %t21, i64* @sll, align 8
43 store i64 %t31, i64* @sll, align 8
47 store i64 %t41, i64* @sll, align 8
51 store i64 %t51, i64* @sll, align 8
63 store i64 %t01, i64* @sll, align 8
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/
H A Dbitreverse.ll9 ; MIPS32-NEXT: sll $2, $4, 24
13 ; MIPS32-NEXT: sll $2, $2, 8
22 ; MIPS32-NEXT: sll $2, $2, 4
29 ; MIPS32-NEXT: sll $2, $2, 2
36 ; MIPS32-NEXT: sll $2, $2, 1
83 ; MIPS32-NEXT: sll $2, $2, 8
92 ; MIPS32-NEXT: sll $2, $2, 4
99 ; MIPS32-NEXT: sll $2, $2, 2
106 ; MIPS32-NEXT: sll $2, $2, 1
113 ; MIPS32-NEXT: sll $7, $7, 8
[all …]
H A Dbswap.ll9 ; MIPS32-NEXT: sll $2, $4, 24
13 ; MIPS32-NEXT: sll $2, $2, 8
36 ; MIPS32-NEXT: sll $2, $5, 24
40 ; MIPS32-NEXT: sll $2, $2, 8
45 ; MIPS32-NEXT: sll $3, $4, 24
49 ; MIPS32-NEXT: sll $3, $3, 8
H A Drem_and_div.ll8 ; MIPS32-NEXT: sll $1, $5, 24
10 ; MIPS32-NEXT: sll $1, $4, 24
15 ; MIPS32-NEXT: sll $1, $1, 24
27 ; MIPS32-NEXT: sll $1, $5, 16
29 ; MIPS32-NEXT: sll $1, $4, 16
34 ; MIPS32-NEXT: sll $1, $1, 16
84 ; MIPS32-NEXT: sll $1, $5, 24
86 ; MIPS32-NEXT: sll $1, $4, 24
91 ; MIPS32-NEXT: sll $1, $1, 24
103 ; MIPS32-NEXT: sll $1, $5, 16
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Durem-seteq-illegal-types.ll16 ; MIPS64EL-NEXT: sll $1, $4, 0
17 ; MIPS64EL-NEXT: sll $2, $1, 1
19 ; MIPS64EL-NEXT: sll $3, $1, 4
21 ; MIPS64EL-NEXT: sll $3, $1, 6
23 ; MIPS64EL-NEXT: sll $3, $1, 8
25 ; MIPS64EL-NEXT: sll $3, $1, 10
43 ; MIPSEL-NEXT: sll $2, $1, 26
82 ; MIPSEL-NEXT: sll $1, $4, 1
108 ; MIPSEL-NEXT: sll $1, $4, 1
110 ; MIPSEL-NEXT: sll $2, $4, 4
[all …]
H A Dconst-mult.ll9 ; MIPS32-NEXT: sll $1, $4, 2
15 ; MIPS64-NEXT: sll $1, $4, 2
26 ; MIPS32-NEXT: sll $1, $4, 2
28 ; MIPS32-NEXT: sll $2, $4, 5
34 ; MIPS64-NEXT: sll $1, $4, 2
36 ; MIPS64-NEXT: sll $2, $4, 5
47 ; MIPS32-NEXT: sll $1, $4, 2
49 ; MIPS32-NEXT: sll $2, $4, 31
55 ; MIPS64-NEXT: sll $1, $4, 2
68 ; MIPS32-NEXT: sll $1, $4, 1
[all …]
H A Dmadd-msub.ll45 ; 64-NEXT: sll $1, $4, 0
46 ; 64-NEXT: sll $2, $5, 0
49 ; 64-NEXT: sll $2, $6, 0
55 ; 64R6-NEXT: sll $1, $4, 0
56 ; 64R6-NEXT: sll $2, $5, 0
58 ; 64R6-NEXT: sll $2, $6, 0
176 ; 64-NEXT: sll $1, $4, 0
177 ; 64-NEXT: sll $2, $5, 0
231 ; 64-NEXT: sll $1, $5, 0
232 ; 64-NEXT: sll $2, $4, 0
[all …]
H A Dsrem-seteq-illegal-types.ll26 ; MIPS64EL-NEXT: sll $2, $4, 0
46 ; MIPSEL-NEXT: sll $1, $4, 28
48 ; MIPSEL-NEXT: sll $2, $1, 1
55 ; MIPSEL-NEXT: sll $2, $1, 1
56 ; MIPSEL-NEXT: sll $1, $1, 2
66 ; MIPS64EL-NEXT: sll $1, $4, 0
69 ; MIPS64EL-NEXT: sll $3, $2, 1
76 ; MIPS64EL-NEXT: sll $4, $2, 1
77 ; MIPS64EL-NEXT: sll $2, $2, 2
92 ; MIPSEL-NEXT: sll $1, $4, 26
[all …]
H A Dunalignedload.ll22 ; MIPS32-EL-DAG: sll $[[T0:[0-9]+]], $[[PART2]], 8
27 ; MIPS32-EB-DAG: sll $[[T0:[0-9]+]], $[[PART1]], 8
29 ; MIPS32-EB-DAG: sll $4, $[[T1]], 16
48 ; MIPS32-EL-DAG: sll $[[T3:[0-9]+]], $[[T1]], 8
50 ; MIPS32-EL-DAG: sll $[[T5:[0-9]+]], $[[T2]], 16
58 ; MIPS32-EB-DAG: sll $[[T3:[0-9]+]], $[[T0]], 8
60 ; MIPS32-EB-DAG: sll $[[T5:[0-9]+]], $[[T4]], 16
61 ; MIPS32-EB-DAG: sll $[[T6:[0-9]+]], $[[T2]], 8
68 ; MIPS32R6-EL-DAG: sll $[[T2:[0-9]+]], $[[T1]], 16
75 ; MIPS32R6-EB-DAG: sll $[[T2:[0-9]+]], $[[T0]], 16
[all …]
H A Dfunnel-shift.ll23 ; CHECK-NEXT: sll $2, $4, 16
204 ; CHECK-NEXT: sll $2, $4, 9
217 ; CHECK-NEXT: sll $2, $4, 9
230 ; CHECK-BE-NEXT: sll $2, $5, 9
233 ; CHECK-BE-NEXT: sll $3, $6, 9
240 ; CHECK-LE-NEXT: sll $2, $7, 9
243 ; CHECK-LE-NEXT: sll $3, $4, 9
269 ; CHECK-NEXT: sll $2, $4, 16
283 ; CHECK-NEXT: sll $2, $4, 1
449 ; CHECK-NEXT: sll $2, $4, 23
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Dmicromips-shift-instructions.s10 # CHECK-EL: sll $4, $3, 7 # encoding: [0x83,0x00,0x00,0x38]
24 # CHECK-EL: sll $3, $3, 7 # encoding: [0x63,0x00,0x00,0x38]
30 # CHECK-EB: sll $4, $3, 7 # encoding: [0x00,0x83,0x38,0x00]
44 # CHECK-EB: sll $3, $3, 7 # encoding: [0x00,0x63,0x38,0x00]
47 sll $4, $3, 7
55 sll $2, $3, $5
58 sll $2, $3
61 sll $3, 7
H A Dmips-expansions.s304 # CHECK-BE: sll $1, $1, 8 # encoding: [0x00,0x01,0x0a,0x00]
308 # CHECK-LE: sll $1, $1, 8 # encoding: [0x00,0x0a,0x01,0x00]
314 # CHECK-BE: sll $1, $1, 8 # encoding: [0x00,0x01,0x0a,0x00]
318 # CHECK-LE: sll $1, $1, 8 # encoding: [0x00,0x0a,0x01,0x00]
325 # CHECK-BE: sll $8, $8, 8 # encoding: [0x00,0x08,0x42,0x00]
330 # CHECK-LE: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00]
336 # CHECK-BE: sll $1, $1, 8 # encoding: [0x00,0x01,0x0a,0x00]
340 # CHECK-LE: sll $1, $1, 8 # encoding: [0x00,0x0a,0x01,0x00]
347 # CHECK-BE: sll $8, $8, 8 # encoding: [0x00,0x08,0x42,0x00]
352 # CHECK-LE: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00]
[all …]
H A Drotations32.s30 # CHECK-32: sll $1, $4, 1 # encoding: [0x00,0x04,0x08,0x40]
35 # CHECK-32: sll $1, $5, 1 # encoding: [0x00,0x05,0x08,0x40]
40 # CHECK-32: sll $1, $4, 2 # encoding: [0x00,0x04,0x08,0x80]
45 # CHECK-32: sll $1, $5, 2 # encoding: [0x00,0x05,0x08,0x80]
70 # CHECK-32: sll $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc0]
75 # CHECK-32: sll $4, $5, 31 # encoding: [0x00,0x05,0x27,0xc0]
80 # CHECK-32: sll $4, $4, 30 # encoding: [0x00,0x04,0x27,0x80]
85 # CHECK-32: sll $4, $5, 30 # encoding: [0x00,0x05,0x27,0x80]
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Drotl-rotr.ll21 ; RV32I-NEXT: sll a1, a0, a1
55 ; RV32I-NEXT: sll a0, a0, a2
90 ; RV32I-NEXT: sll a1, a0, a5
93 ; RV32I-NEXT: sll a1, a4, a2
115 ; RV32I-NEXT: sll a4, a4, a7
121 ; RV32I-NEXT: sll a0, a0, a2
129 ; RV64I-NEXT: sll a1, a0, a1
200 ; RV32I-NEXT: sll a3, a6, a3
206 ; RV32I-NEXT: sll a3, a4, a6
214 ; RV32I-NEXT: sll a6, a1, a6
[all …]
H A Dshifts.ll26 ; RV32I-NEXT: sll a3, a4, a3
70 ; RV32I-NEXT: sll a3, a4, a3
107 ; RV32I-NEXT: sll a1, a0, a3
111 ; RV32I-NEXT: sll a1, a1, a2
116 ; RV32I-NEXT: sll a0, a0, a2
121 ; RV64I-NEXT: sll a0, a0, a1
139 ; RV64I-NEXT: sll a0, a0, a1
155 ; RV32I-NEXT: sll t0, a5, a6
161 ; RV32I-NEXT: sll a6, a4, a6
203 ; RV32I-NEXT: sll t5, t5, t2
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dshift-01.ll10 ; CHECK-NEXT: sll %r2, 1
20 ; CHECK-NEXT: sll %r2, 31
40 ; CHECK-NEXT: sll %r2, 0(%r3)
51 ; CHECK-NEXT: sll %r2, 0(%r3)
61 ; CHECK-NEXT: sll %r2, 10(%r3)
72 ; CHECK-NEXT: sll %r2, 10(%r3)
85 ; CHECK-NEXT: sll %r2, 4095(%r3)
97 ; CHECK-NEXT: sll %r2, 0(%r3)
109 ; CHECK-NEXT: sll %r2, 0(%r3)
121 ; CHECK-NEXT: sll %r2, 0(%r1)
/llvm-project-15.0.7/llvm/test/CodeGen/LoongArch/ir-instruction/
H A Dshl.ll21 ; LA32-NEXT: sll.w $a0, $a0, $a1
26 ; LA64-NEXT: sll.d $a0, $a0, $a1
35 ; LA32-NEXT: sll.w $a0, $a0, $a1
40 ; LA64-NEXT: sll.d $a0, $a0, $a1
49 ; LA32-NEXT: sll.w $a0, $a0, $a1
54 ; LA64-NEXT: sll.w $a0, $a0, $a1
66 ; LA32-NEXT: sll.w $a1, $a1, $a2
71 ; LA32-NEXT: sll.w $a5, $a0, $a3
74 ; LA32-NEXT: sll.w $a0, $a0, $a2
81 ; LA64-NEXT: sll.d $a0, $a0, $a1
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/Fast-ISel/
H A Dcallabi.ll15 ; 32R1: sll $[[T1:[0-9]+]], $[[T0]], 24
30 ; 32R1: sll $[[T1:[0-9]+]], $[[T0]], 16
58 ; 32R1-DAG: sll $[[T2:[0-9]+]], $[[T0]], 24
170 ; 32R1: sll $[[R1:[0-9]+]], $[[R1]], 24
173 ; 32R1: sll $[[R2]], $[[R2]], 24
176 ; 32R1: sll $[[R3]], $[[R3]], 24
179 ; 32R1: sll $[[R4]], $[[R4]], 24
199 ; 32R1: sll $[[R1]], $[[R1]], 16
202 ; 32R1: sll $[[R2]], $[[R2]], 16
205 ; 32R1: sll $[[R3]], $[[R3]], 16
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/msa/
H A Dimmediates.ll23 ; MSA64N32-NEXT: sll $1, $4, 0
45 ; MSA64N32-NEXT: sll $1, $4, 0
67 ; MSA64N32-NEXT: sll $1, $4, 0
90 ; MSA64N32-NEXT: sll $1, $4, 0
91 ; MSA64N32-NEXT: sll $2, $5, 0
116 ; MSA64N32-NEXT: sll $1, $4, 0
117 ; MSA64N32-NEXT: sll $2, $5, 0
142 ; MSA64N32-NEXT: sll $1, $4, 0
143 ; MSA64N32-NEXT: sll $2, $5, 0
168 ; MSA64N32-NEXT: sll $1, $5, 0
[all …]

12345678910>>...12