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Searched refs:size4 (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/libcxx/test/std/utilities/intseq/intseq.general/
H A Dinteger_seq.pass.cpp31 using size4 = std::make_index_sequence<4>; // generates size_t: 0,1,2,3 in main() typedef
43 static_assert ( std::is_same<size4::value_type, size_t>::value, "size4 type wrong" ); in main()
44 static_assert ( size4::size () == 4, "size4 size wrong" ); in main()
66 auto t4 = extract ( tup, size4 ()); in main()
67 static_assert ( std::tuple_size<decltype(t4)>::value == size4::size (), "t4 size wrong"); in main()
/llvm-project-15.0.7/lld/test/ELF/lto/
H A Dweak.ll10 ; RUN: llc %t/size4.ll -o %t-size4.o -filetype=obj
18 ; RUN: ld.lld %t-size1.bc %t-size4.o -o %t3.so -shared
21 ; RUN: ld.lld %t-size4.o %t-size1.bc -o %t4.so -shared
44 ;--- size4.ll
/llvm-project-15.0.7/flang/test/Evaluate/
H A Dfolding21.f9019 integer, parameter :: size4 = size(nada4) local
28 logical, parameter :: test_size_4 = size4 == 0
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A DRedundantstore.ll17 %size4 = bitcast i8* %add.ptr3 to i32*
18 store i32 %conv2, i32* %size4, align 4
/llvm-project-15.0.7/llvm/test/Transforms/PhaseOrdering/X86/
H A Dspurious-peeling.ll106 …%size4 = getelementptr inbounds %class.HomemadeVector.0, %class.HomemadeVector.0* %call, i32 0, i3…
107 %1 = load i32, i32* %size4, align 8, !tbaa !6
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Denqueue-kernel.ll64 …%block.size4 = getelementptr inbounds <{ i32, i32, i8 addrspace(1)*, i64 addrspace(1)*, i64, i8 }>…
65 store i32 41, i32 addrspace(5)* %block.size4, align 8
/llvm-project-15.0.7/mlir/test/Dialect/Tensor/
H A Dcanonicalize.mlir314 func.func @static_tensor.generate(%size1: index, %size4: index) -> tensor<3x?x?x7x?xindex> {
317 %0 = tensor.generate %size1, %c5, %size4 {