| /llvm-project-15.0.7/llvm/test/CodeGen/X86/ |
| H A D | x86-64-double-shifts-var.ll | 20 ; double precision shift instructions we do not generate 'shld' or 'shrd'
47 ; CHECK-NOT: shrd
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| H A D | x86-64-double-precision-shift-right.ll | 6 ; of instructions with lower latencies instead of shrd instruction.
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| H A D | shift-double.ll | 483 ; These are not valid shld/shrd patterns. When the shift amount modulo
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| H A D | funnel-shift.ll | 857 ; With constant shift amount, this is 'shrd' or 'shld'.
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| /llvm-project-15.0.7/llvm/test/MC/X86/ |
| H A D | intel-syntax.s | 456 shrd DX, BX define
457 shrd DX, BX, CL define
458 shrd DX, BX, 1 define
459 shrd [RAX], BX label
460 shrd [RAX], BX, CL label
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| H A D | x86-64.s | 379 shrd %bx, %dx label
380 shrd %cl, %bx, %dx label
381 shrd $1, %bx, %dx label
382 shrd %bx, (%rax) label
383 shrd %cl, %bx, (%rax) label
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InstrShiftRotate.td | 668 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
678 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
688 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
704 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
718 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
732 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
745 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
754 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
763 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
777 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[all …]
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| H A D | X86InstrInfo.td | 3639 // shld/shrd op,op -> shld op, op, CL
3643 def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>;
3644 def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>;
3645 def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>;
3650 def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>;
3651 def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>;
3652 def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>;
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| H A D | README.txt | 1272 sra, srl, shld, shrd, atomic ops, and others. It is also currently not done
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| /llvm-project-15.0.7/llvm/test/Instrumentation/AddressSanitizer/X86/ |
| H A D | bug_11395.ll | 63 …x, %edx\0A\09mov %esi, %eax\0A\09movzbl $7 , %ecx\0A\09shrd %cl, %edx, %eax\…
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