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/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Dcombine-min-max.ll13 ret i32 %sel
22 ret i64 %sel
34 ret i16 %sel
42 ret i16 %sel
50 ret i16 %sel
58 ret i16 %sel
67 ret i16 %sel
75 ret i16 %sel
83 ret i16 %sel
91 ret i16 %sel
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/SystemZ/
H A Dcmpsel.ll12 ret i8 %sel
23 ret i16 %sel
34 ret i32 %sel
45 ret i64 %sel
78 ret i8 %sel
89 ret i16 %sel
100 ret i32 %sel
111 ret i64 %sel
144 ret i8 %sel
155 ret i16 %sel
[all …]
H A Dscalar-cmp-cmp-log-sel.ll13 ret i8 %sel
28 ret i16 %sel
43 ret i32 %sel
58 ret i64 %sel
103 ret i8 %sel
118 ret i16 %sel
133 ret i32 %sel
148 ret i64 %sel
193 ret i8 %sel
283 ret i8 %sel
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dselect_const.ll16 ret i32 %sel
25 ret i32 %sel
35 ret i32 %sel
46 ret i32 %sel
54 ret i32 %sel
63 ret i32 %sel
75 ret i32 %sel
84 ret i32 %sel
93 ret i32 %sel
104 ret i32 %sel
[all …]
H A Dsve-vselect-imm.ll11 ret <vscale x 16 x i8> %sel
21 ret <vscale x 8 x i16> %sel
31 ret <vscale x 4 x i32> %sel
41 ret <vscale x 2 x i64> %sel
51 ret <vscale x 16 x i8> %sel
61 ret <vscale x 8 x i16> %sel
71 ret <vscale x 4 x i32> %sel
81 ret <vscale x 2 x i64> %sel
91 ret <vscale x 8 x i16> %sel
101 ret <vscale x 4 x i32> %sel
[all …]
H A Dsve-fixed-length-int-vselect.ll17 ret <8 x i8> %sel
29 ret <16 x i8> %sel
46 store <32 x i8> %sel, <32 x i8>* %a
80 store <64 x i8> %sel, <64 x i8>* %a
129 ret <4 x i16> %sel
142 ret <8 x i16> %sel
242 ret <2 x i32> %sel
255 ret <4 x i32> %sel
272 store <8 x i32> %sel, <8 x i32>* %a
356 ret <1 x i64> %sel
[all …]
H A Dsve-select.ll205 ret <vscale x 16 x i8> %sel
214 ret <vscale x 8 x i16> %sel
223 ret <vscale x 4 x i32> %sel
233 ret <vscale x 1 x i64> %sel
242 ret <vscale x 2 x i64> %sel
380 ret <vscale x 1 x i64> %sel
394 ret <vscale x 2 x i64> %sel
408 ret <vscale x 1 x i32> %sel
422 ret <vscale x 4 x i32> %sel
464 ret <vscale x 1 x i8> %sel
[all …]
H A Dsve-intrinsics-sel.ll12 ; CHECK-NEXT: sel p0.b, p0, p1.b, p2.b
14 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.sel.nxv16i1(<vscale x 16 x i1> %pg,
23 ; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b
25 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg,
34 ; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
45 ; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
56 ; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
67 ; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
78 ; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
89 ; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dselect-to-branch.mir9 ret i32 %sel
16 ; CHECK-NEXT: ret i32 %sel
22 ret i32 %sel
35 ; CHECK-NEXT: ret i32 %sel
41 ret i32 %sel
53 ; CHECK-NEXT: ret i32 %sel
59 ret i32 %sel
65 ; CHECK-NEXT: ret i32 %sel
72 ret i32 %sel
78 ; CHECK-NEXT: ret i32 %sel
[all …]
H A Dselect_const.ll17 ret i32 %sel
26 ret i32 %sel
36 ret i32 %sel
47 ret i32 %sel
55 ret i32 %sel
64 ret i32 %sel
76 ret i32 %sel
85 ret i32 %sel
94 ret i32 %sel
106 ret i32 %sel
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dselect_const.ll17 ret i32 %sel
27 ret i32 %sel
38 ret i32 %sel
50 ret i32 %sel
59 ret i32 %sel
69 ret i32 %sel
82 ret i32 %sel
92 ret i32 %sel
102 ret i32 %sel
115 ret i32 %sel
[all …]
/llvm-project-15.0.7/llvm/test/MC/AArch64/SVE/
H A Dsel.s12 sel p0.b, p0, p0.b, p0.b label
18 sel p15.b, p15, p15.b, p15.b label
24 sel z31.b, p15, z31.b, z31.b label
30 sel z31.h, p15, z31.h, z31.h label
36 sel z31.s, p15, z31.s, z31.s label
42 sel z31.d, p15, z31.d, z31.d label
48 sel z23.s, p11, z13.s, z8.s label
54 sel z23.d, p11, z13.d, z8.d label
60 sel z23.h, p11, z13.h, z8.h label
66 sel z23.b, p11, z13.b, z8.b label
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dsmin-icmp.ll19 %cmp2 = icmp eq i32 %sel, %x
32 %cmp2 = icmp eq i32 %sel, %x
47 %cmp2 = icmp eq i32 %x, %sel
62 %cmp2 = icmp eq i32 %x, %sel
75 %cmp2 = icmp sge i32 %sel, %x
88 %cmp2 = icmp sge i32 %sel, %x
103 %cmp2 = icmp sle i32 %x, %sel
131 %cmp2 = icmp ne i32 %sel, %x
144 %cmp2 = icmp ne i32 %sel, %x
159 %cmp2 = icmp ne i32 %x, %sel
[all …]
H A Dunsigned_saturated_sub.ll21 ret i64 %sel
34 ret i64 %sel
48 ret i64 %sel
62 ret i64 %sel
79 ret i64 %sel
111 ret i64 %sel
128 ret i64 %sel
141 ret i64 %sel
159 ret i64 %sel
173 ret i64 %sel
[all …]
H A Dicmp-select.ll17 %cmp2 = icmp eq i8 %sel, 0
30 %cmp2 = icmp eq i8 %sel, %z
45 %cmp2 = icmp eq i8 %z, %sel
61 %cmp2 = icmp eq i8 %z, %sel
73 %cmp2 = icmp eq i8 %sel, %z
87 call void @use(i8 %sel)
88 %cmp2 = icmp eq i8 %sel, %z
103 call void @use(i8 %sel)
104 %cmp2 = icmp eq i8 %sel, %z
117 %cmp2 = icmp ne i8 %sel, %z
[all …]
H A Dunordered-fcmp-select.ll12 ret float %sel
23 ret float %sel
33 ret float %sel
44 ret float %sel
55 ret float %sel
65 ret float %sel
76 ret float %sel
87 ret float %sel
98 ret float %sel
109 ret float %sel
[all …]
H A Dsmax-icmp.ll20 %cmp2 = icmp eq i32 %sel, %x
33 %cmp2 = icmp eq i32 %sel, %x
48 %cmp2 = icmp eq i32 %x, %sel
63 %cmp2 = icmp eq i32 %x, %sel
76 %cmp2 = icmp sle i32 %sel, %x
89 %cmp2 = icmp sle i32 %sel, %x
104 %cmp2 = icmp sge i32 %x, %sel
132 %cmp2 = icmp ne i32 %sel, %x
145 %cmp2 = icmp ne i32 %sel, %x
160 %cmp2 = icmp ne i32 %x, %sel
[all …]
H A Dumin-icmp.ll20 %cmp2 = icmp eq i32 %sel, %x
33 %cmp2 = icmp eq i32 %sel, %x
48 %cmp2 = icmp eq i32 %x, %sel
63 %cmp2 = icmp eq i32 %x, %sel
76 %cmp2 = icmp uge i32 %sel, %x
89 %cmp2 = icmp uge i32 %sel, %x
104 %cmp2 = icmp ule i32 %x, %sel
132 %cmp2 = icmp ne i32 %sel, %x
145 %cmp2 = icmp ne i32 %sel, %x
160 %cmp2 = icmp ne i32 %x, %sel
[all …]
H A Dumax-icmp.ll20 %cmp2 = icmp eq i32 %sel, %x
33 %cmp2 = icmp eq i32 %sel, %x
48 %cmp2 = icmp eq i32 %x, %sel
63 %cmp2 = icmp eq i32 %x, %sel
76 %cmp2 = icmp ule i32 %sel, %x
89 %cmp2 = icmp ule i32 %sel, %x
104 %cmp2 = icmp uge i32 %x, %sel
132 %cmp2 = icmp ne i32 %sel, %x
145 %cmp2 = icmp ne i32 %sel, %x
160 %cmp2 = icmp ne i32 %x, %sel
[all …]
H A Dselect-obo-peo-ops.ll423 ret i32 %sel
436 ret i32 %sel
449 ret i32 %sel
462 ret i32 %sel
475 ret i32 %sel
488 ret i32 %sel
501 ret i32 %sel
514 ret i32 %sel
527 ret i32 %sel
540 ret i32 %sel
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/AArch64/
H A Dshuffle-select.ll4 ; COST-LABEL: sel.v8i8
6 ; CODE-LABEL: sel.v8i8
13 ; COST-LABEL: sel.v16i8
15 ; CODE-LABEL: sel.v16i8
22 ; COST-LABEL: sel.v4i16
24 ; CODE-LABEL: sel.v4i16
32 ; COST-LABEL: sel.v8i16
34 ; CODE-LABEL: sel.v8i16
41 ; COST-LABEL: sel.v2i32
43 ; CODE-LABEL: sel.v2i32
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SCCP/
H A Dip-ranges-select.ll27 %c.2 = icmp eq i32 %sel, 0
50 %c.1 = icmp sgt i32 %sel.1, 300
51 %c.2 = icmp sgt i32 %sel.1, 100
52 %c.3 = icmp eq i32 %sel.1, 50
53 %c.4 = icmp slt i32 %sel.1, 9
87 %c.1 = icmp sgt i32 %sel.1, 300
88 %c.2 = icmp sgt i32 %sel.1, 100
89 %c.3 = icmp eq i32 %sel.1, 50
90 %c.4 = icmp slt i32 %sel.1, 9
115 ; CHECK-NEXT: ret i32 %sel.1
[all …]
H A Dselect.ll21 ; CHECK-NEXT: %sel.1 = select i1 %cmp, i32 %x, i32 10
22 ; CHECK-NEXT: %c.1 = icmp sgt i32 %sel.1, 300
23 ; CHECK-NEXT: %c.2 = icmp sgt i32 %sel.1, 100
24 ; CHECK-NEXT: %c.3 = icmp eq i32 %sel.1, 50
25 ; CHECK-NEXT: %c.4 = icmp slt i32 %sel.1, 9
31 %sel.1 = select i1 %cmp, i32 %x, i32 10
32 %c.1 = icmp sgt i32 %sel.1, 300
33 %c.2 = icmp sgt i32 %sel.1, 100
34 %c.3 = icmp eq i32 %sel.1, 50
35 %c.4 = icmp slt i32 %sel.1, 9
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dvec-cmpsel.ll15 ret <2 x i8> %sel
27 ret <2 x i16> %sel
38 ret <16 x i8> %sel
53 ret <16 x i16> %sel
66 ret <32 x i8> %sel
78 ret <2 x i8> %sel
89 ret <2 x i16> %sel
101 ret <2 x i32> %sel
113 ret <8 x i8> %sel
124 ret <8 x i16> %sel
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Ddagcombine-select.ll115 %bo = sub i32 5, %sel
124 %bo = sub i16 5, %sel
134 %bo = sub i16 1, %sel
165 %bo = sdiv i64 120, %sel
174 %bo = sdiv i32 184, %sel
183 %bo = udiv i64 120, %sel
192 %bo = srem i64 33, %sel
201 %bo = urem i64 33, %sel
210 %bo = shl i32 1, %sel
219 %bo = lshr i32 64, %sel
[all …]

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