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/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dppc64-r2-alloc.ll7 %div = sdiv i32 %a, %d
8 %div1 = sdiv i32 %div, %d
9 %div2 = sdiv i32 %div1, %d
10 %div3 = sdiv i32 %div2, %d
11 %div4 = sdiv i32 %div3, %d
12 %div5 = sdiv i32 %div4, %d
13 %div6 = sdiv i32 %div5, %d
14 %div7 = sdiv i32 %div6, %d
15 %div8 = sdiv i32 %div7, %d
16 %div9 = sdiv i32 %div8, %d
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dadd-shl-sdiv-to-srem.ll4 define i8 @add-shl-sdiv-scalar0(i8 %x) {
5 ; CHECK-LABEL: @add-shl-sdiv-scalar0(
9 %sd = sdiv i8 %x, -4
20 %sd = sdiv i8 %x, -64
31 %sd = sdiv i32 %x, -1073741824
82 %sd = sdiv i32 %x, -16
95 %sd = sdiv i32 %x, -16
110 %sd = sdiv i32 %x, -16
126 %sd = sdiv i32 %x, -16
158 %sd = sdiv i8 %x, 4
[all …]
H A Dsdiv-canonicalize.ll15 %sdiv = sdiv i32 %neg, %y
16 ret i32 %sdiv
26 %sdiv = sdiv exact i32 %neg, %y
27 ret i32 %sdiv
40 %sdiv = sdiv i32 %y, %neg
41 ret i32 %sdiv
51 %sdiv = sdiv i32 %neg, %y
52 ret i32 %sdiv
62 %sdiv = sdiv <2 x i32> %neg, %y
74 %sdiv = sdiv i32 %neg, %y
[all …]
H A Ddiv.ll10 %B = sdiv i32 %A, 1
28 %B = sdiv i32 %A, -1
55 %div = sdiv i32 %y, %sext
305 %A = sdiv i32 1, %x
735 %r = sdiv i8 %x, %a
1101 %r = sdiv i32 42, %s
1114 %r = sdiv i32 42, %s
1123 %r = sdiv i32 42, %s
1136 %r = sdiv i32 42, %s
1314 %A = sdiv i32 1, %x
[all …]
H A Dsdiv-exact-by-power-of-two.ll15 %div = sdiv exact i8 %x, 32
20 ; CHECK-NEXT: [[DIV:%.*]] = sdiv i8 [[X:%.*]], 32
23 %div = sdiv i8 %x, 32 ; not exact
32 %div = sdiv i8 %x, 128 ; negative divisor
41 %div = sdiv exact <2 x i8> %x, <i8 32, i8 32>
50 %div = sdiv exact <2 x i8> %x, <i8 32, i8 16>
58 %div = sdiv exact <2 x i8> %x, <i8 32, i8 undef>
63 ; CHECK-NEXT: [[DIV:%.*]] = sdiv exact <2 x i8> [[X:%.*]], <i8 32, i8 -128>
66 %div = sdiv exact <2 x i8> %x, <i8 32, i8 128> ; non-non-negative divisor
H A Dsrem-via-sdiv-mul-sub.ll19 ; CHECK-NEXT: [[DIV:%.*]] = sdiv i8 [[X:%.*]], [[Y:%.*]]
25 %div = sdiv i8 %x, %y
40 %div = sdiv <2 x i8> %x, %y
51 ; CHECK-NEXT: [[DIV:%.*]] = sdiv i8 [[X:%.*]], [[Y:%.*]]
58 %div = sdiv i8 %x, %y
73 ; CHECK-NEXT: [[DIV:%.*]] = sdiv i8 [[X:%.*]], [[Y]]
80 %div = sdiv i8 %x, %y
91 ; CHECK-NEXT: [[DIV:%.*]] = sdiv i8 [[X0:%.*]], [[Y:%.*]]
97 %div = sdiv i8 %x0, %y
106 ; CHECK-NEXT: [[DIV:%.*]] = sdiv i8 [[X:%.*]], [[Y0:%.*]]
[all …]
H A Dsigned-mul-overflow-check-via-mul-sdiv.ll16 %t1 = sdiv i8 %t0, %x
28 %t1 = sdiv <2 x i8> %t0, %x
44 %t1 = sdiv i8 %t0, %x
58 %t1 = sdiv i8 %t0, %x
72 %t1 = sdiv i8 %t0, %x
91 %t1 = sdiv i8 %t0, %x
105 %t1 = sdiv i8 %t0, %x
122 %t1 = sdiv i8 %t0, %x
138 %t1 = sdiv i8 %t0, %x1
151 %t1 = sdiv i8 %t0, %x
[all …]
H A Dsdiv-exact-by-negative-power-of-two.ll15 %div = sdiv exact i8 %x, -32
20 ; CHECK-NEXT: [[DIV:%.*]] = sdiv i8 [[X:%.*]], -32
23 %div = sdiv i8 %x, -32 ; not exact
33 %div = sdiv exact <2 x i8> %x, <i8 -32, i8 -32>
43 %div = sdiv exact <2 x i8> %x, <i8 -32, i8 -16>
49 ; CHECK-NEXT: [[DIV:%.*]] = sdiv exact <2 x i8> [[X:%.*]], <i8 -32, i8 16>
52 %div = sdiv exact <2 x i8> %x, <i8 -32, i8 16>
60 %div = sdiv exact <2 x i8> %x, <i8 -32, i8 undef>
/llvm-project-15.0.7/llvm/test/Analysis/Lint/
H A Dcheck-zero-divide.ll4 %b = sdiv <2 x i32> %a, <i32 5, i32 8>
25 ; CHECK-NEXT: %b = sdiv i32 %a, 0
26 %b = sdiv i32 %a, 0
32 ; CHECK-NEXT: %b = sdiv i32 %a, 0
33 %b = sdiv i32 %a, zeroinitializer
40 %b = sdiv <2 x i32> %a, <i32 0, i32 5>
47 %b = sdiv <2 x i32> %a, <i32 4, i32 0>
54 %b = sdiv <2 x i32> %a, <i32 0, i32 0>
61 %b = sdiv <2 x i32> %a, <i32 undef, i32 5>
68 %b = sdiv <2 x i32> %a, <i32 5, i32 undef>
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Ddiv-rem-pair-recomposition-signed.ll15 ; ALL-NEXT: sdiv w8, w9, w8
19 %div = sdiv i8 %x, %y
31 ; ALL-NEXT: sdiv w8, w9, w8
35 %div = sdiv i16 %x, %y
45 ; ALL-NEXT: sdiv w8, w0, w1
49 %div = sdiv i32 %x, %y
59 ; ALL-NEXT: sdiv x8, x0, x1
63 %div = sdiv i64 %x, %y
257 %div = sdiv i32 %x, %y
274 %div = sdiv i32 %x, %y
[all …]
H A Drem_crash.ll13 %0 = sdiv i8 %x, 10
29 %0 = sdiv i8 %x, 10
45 %0 = sdiv i16 %x, 10
61 %0 = sdiv i16 %x, 10
77 %0 = sdiv i32 %x, 10
93 %0 = sdiv i32 %x, 10
109 %0 = sdiv i64 %x, 10
125 %0 = sdiv i64 %x, 10
141 %0 = sdiv i8 %x, 10
157 %0 = sdiv i8 %x, 10
[all …]
H A Darm64-arith.ll33 ; CHECK: sdiv w0, w0, w1
35 %sdiv = sdiv i32 %a, %b
36 ret i32 %sdiv
42 ; CHECK: sdiv x0, x0, x1
44 %sdiv = sdiv i64 %a, %b
45 ret i64 %sdiv
169 ; CHECK: sdiv w0, w0, w1
171 %sdiv = call i32 @llvm.aarch64.sdiv.i32(i32 %a, i32 %b)
172 ret i32 %sdiv
180 %sdiv = call i64 @llvm.aarch64.sdiv.i64(i64 %a, i64 %b)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dsdiv-pow2-thumb-size.ll7 ; Armv6m targets don't have a sdiv instruction, so sdiv should not appear at
11 ; V6M-NOT: sdiv
14 ; Test sdiv i16
23 %0 = sdiv i16 %F, 2
35 %div = sdiv i32 %F, 4
47 %div = sdiv i32 %F, 5
55 ; CHECK-NOT: sdiv
57 %div = sdiv i32 %F, 256
65 ; the sdiv to sdiv, but to the faster instruction sequence.
84 %0 = sdiv i16 %F, 2
[all …]
H A Drem_crash.ll13 %0 = sdiv i8 %x, 10
29 %0 = sdiv i8 %x, 10
45 %0 = sdiv i16 %x, 10
61 %0 = sdiv i16 %x, 10
77 %0 = sdiv i32 %x, 10
93 %0 = sdiv i32 %x, 10
109 %0 = sdiv i64 %x, 10
125 %0 = sdiv i64 %x, 10
141 %0 = sdiv i8 %x, 10
157 %0 = sdiv i8 %x, 10
[all …]
H A Dsdiv-pow2-arm-size.ll17 ; Try an i16 sdiv, with a small immediate.
22 ; DIV-NEXT: sdiv r0, r0, r1
33 %0 = sdiv i16 %F, 2
37 ; Try an i32 sdiv, with a small immediate.
42 ; DIV-NEXT: sdiv r0, r0, r1
51 %div = sdiv i32 %F, 4
60 ; DIV-NEXT: sdiv r0, r0, r1
63 %div = sdiv i32 %F, 131072
75 %div = sdiv i32 %F, 4
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Dsdiv.ll9 %div = sdiv i32 %negx, %x
18 %div = sdiv <2 x i32> %negx, %x
28 %div = sdiv i32 %xy, %yx
38 %div = sdiv <2 x i32> %xy, %yx
48 %div = sdiv i32 %negx, %x
57 %div = sdiv i32 %x, %negx
68 %div = sdiv i32 %negx, %x
81 %div = sdiv i32 %xy, %yx
94 %div = sdiv i32 %xy, %yx
107 %div = sdiv i32 %xy, %yx
[all …]
H A Dsigned-div-rem.ll9 %div = sdiv i32 %conv, 129
20 %div = sdiv i32 %conv, 128
29 %div = sdiv i32 %conv, -129
40 %div = sdiv i32 %conv, -128
49 %div = sdiv i32 %conv, 256
60 %div = sdiv i32 %conv, 255
89 %div = sdiv i32 %and, 254
100 %div = sdiv i32 %and, 253
129 %div = sdiv i32 %or, 254
140 %div = sdiv i32 %or, 253
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/AArch64/
H A Ddiv.ll4 define i32 @sdiv() {
5 ; CHECK-LABEL: 'sdiv'
39 %I8 = sdiv i8 undef, undef
110 %I64 = sdiv i64 undef, 7
115 %I32 = sdiv i32 undef, 7
120 %I16 = sdiv i16 undef, 7
125 %I8 = sdiv i8 undef, 7
196 %I64 = sdiv i64 undef, 7
201 %I32 = sdiv i32 undef, 7
211 %I8 = sdiv i8 undef, 7
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/AMDGPU/
H A Ddiv.ll13 define i32 @sdiv() {
14 ; FAST-LABEL: 'sdiv'
33 ; SLOW-LABEL: 'sdiv'
52 ; ALL-SIZE-LABEL: 'sdiv'
86 %I8 = sdiv i8 undef, undef
233 %I64 = sdiv i64 undef, 7
238 %I32 = sdiv i32 undef, 7
243 %I16 = sdiv i16 undef, 7
248 %I8 = sdiv i8 undef, 7
410 %I8 = sdiv i8 undef, 7
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/X86/
H A Ddiv.ll14 define i32 @sdiv() {
15 ; CHECK-LABEL: 'sdiv'
34 %I64 = sdiv i64 undef, undef
39 %I32 = sdiv i32 undef, undef
44 %I16 = sdiv i16 undef, undef
49 %I8 = sdiv i8 undef, undef
272 %I64 = sdiv i64 undef, 7
277 %I32 = sdiv i32 undef, 7
282 %I16 = sdiv i16 undef, 7
287 %I8 = sdiv i8 undef, 7
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Drem_crash.ll14 %0 = sdiv i8 %x, 10
30 %0 = sdiv i8 %x, 10
46 %0 = sdiv i16 %x, 10
62 %0 = sdiv i16 %x, 10
78 %0 = sdiv i32 %x, 10
94 %0 = sdiv i32 %x, 10
110 %0 = sdiv i64 %x, 10
126 %0 = sdiv i64 %x, 10
142 %0 = sdiv i8 %x, 10
158 %0 = sdiv i8 %x, 10
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Darith-div-undef.ll16 %ab0 = sdiv i32 %a0, undef
17 %ab1 = sdiv i32 %a1, 4
18 %ab2 = sdiv i32 %a2, 8
19 %ab3 = sdiv i32 %a3, 16
20 %ab4 = sdiv i32 %a4, undef
21 %ab5 = sdiv i32 %a5, 4
22 %ab6 = sdiv i32 %a6, 8
23 %ab7 = sdiv i32 %a7, 16
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Didiv.s13 sdiv r1, r2, r3
15 @ A15-ARM: sdiv r1, r2, r3 @ encoding: [0x12,0xf3,0x11,0xe7]
17 @ A15-THUMB: sdiv r1, r2, r3 @ encoding: [0x92,0xfb,0xf3,0xf1]
20 @ A15-ARM-NOTHUMBHWDIV: sdiv r1, r2, r3 @ encoding: [0x12,0xf3,0x11,0xe7]
22 @ A15-THUMB-NOARMHWDIV: sdiv r1, r2, r3 @ encoding: [0x92,0xfb,0xf3,0xf1]
25 @ ARMV8: sdiv r1, r2, r3 @ encoding: [0x12,0xf3,0x11,0xe7]
27 @ THUMBV8: sdiv r1, r2, r3 @ encoding: [0x92,0xfb,0xf3,0xf1]
30 @ ARMV8-NOTHUMBHWDIV: sdiv r1, r2, r3 @ encoding: [0x12,0xf3,0x11,0xe7]
32 @ THUMBV8-NOTHUMBHWDIV: sdiv r1, r2, r3 @ encoding: [0x92,0xfb,0xf3,0xf1]
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/SystemZ/
H A Ddivrem-pow2.ll9 ; Scalar sdiv
12 %r = sdiv i64 %a, 2
18 %r = sdiv i64 %a, -4
24 %r = sdiv i32 %a, 8
30 %r = sdiv i32 %a, -16
36 %r = sdiv i16 %a, 32
42 %r = sdiv i16 %a, -64
48 %r = sdiv i8 %a, 64
54 %r = sdiv i8 %a, -128
59 ; Vector sdiv
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/GVN/PRE/
H A Dlocal-pre.ll43 %a = sdiv i32 %p, %q
51 ; CHECK-NEXT: %b = sdiv
56 %b = sdiv i32 %p, %q
70 %a = sdiv i32 %p, %q
81 ; CHECK-NEXT: %b = sdiv
86 %b = sdiv i32 %p, %q
104 %a = sdiv i32 %p, 6
117 %b = sdiv i32 %p, 6
132 %a = sdiv i32 %p, %q
136 %b = sdiv i32 %p, %q
[all …]

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