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Searched refs:sad (Results 1 – 9 of 9) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dllvm.amdgcn.sad.hi.u8.ll4 declare i32 @llvm.amdgcn.sad.hi.u8(i32, i32, i32) #0
9 %result= call i32 @llvm.amdgcn.sad.hi.u8(i32 %src, i32 100, i32 100) #0
17 %result= call i32 @llvm.amdgcn.sad.hi.u8(i32 %src, i32 %a, i32 %b) #0
H A Dllvm.amdgcn.sad.u8.ll4 declare i32 @llvm.amdgcn.sad.u8(i32, i32, i32) #0
9 %result= call i32 @llvm.amdgcn.sad.u8(i32 %src, i32 100, i32 100) #0
17 %result= call i32 @llvm.amdgcn.sad.u8(i32 %src, i32 %a, i32 %b) #0
H A Dllvm.amdgcn.sad.u16.ll4 declare i32 @llvm.amdgcn.sad.u16(i32, i32, i32) #0
9 %result= call i32 @llvm.amdgcn.sad.u16(i32 %src, i32 100, i32 100) #0
17 %result= call i32 @llvm.amdgcn.sad.u16(i32 %src, i32 %a, i32 %b) #0
/llvm-project-15.0.7/clang/test/SemaCXX/
H A Dlibstdcxx_pair_swap_hack.cpp81 namespace sad { namespace
/llvm-project-15.0.7/llvm/docs/
H A DExtendedIntegerResults.txt127 the sad truth of the matter is that this is a) unlikely to happen anytime in
/llvm-project-15.0.7/clang/test/CodeGenOpenCL/
H A Dbuiltins-amdgcn.cl724 // CHECK: tail call i32 @llvm.amdgcn.sad.u8(i32 %src0, i32 %src1, i32 %src2)
736 // CHECK: call i32 @llvm.amdgcn.sad.hi.u8(i32 %src0, i32 %src1, i32 %src2)
742 // CHECK: call i32 @llvm.amdgcn.sad.u16(i32 %src0, i32 %src1, i32 %src2)
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dsad.ll977 ; This contains an unrolled sad loop with a non-zero initial value.
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dv60Intrins.ll323 ; CHECK: v{{[0-9]*}}:{{[0-9]*}}.uw = vr{{[0-9]*}}sad(v{{[0-9]*}}:{{[0-9]*}}.ub,r{{[0-9]*}}.ub,#0)
324 ; CHECK: v{{[0-9]*}}:{{[0-9]*}}.uw += vr{{[0-9]*}}sad(v{{[0-9]*}}:{{[0-9]*}}.ub,r{{[0-9]*}}.ub,#0)
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXIntrinsics.td819 def INT_NVVM_SAD_I : F_MATH_3<"sad.s32 \t$dst, $src0, $src1, $src2;",
821 def INT_NVVM_SAD_UI : F_MATH_3<"sad.u32 \t$dst, $src0, $src1, $src2;",