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/llvm-project-15.0.7/llvm/test/MC/AMDGPU/
H A Dgfx9_asm_sop2.s3 s_add_u32 s5, s1, s2
33 s_add_u32 s5, s101, s2
51 s_add_u32 s5, m0, s2
60 s_add_u32 s5, 0, s2
63 s_add_u32 s5, -1, s2
66 s_add_u32 s5, 0.5, s2
105 s_add_u32 s5, s1, m0
114 s_add_u32 s5, s1, 0
117 s_add_u32 s5, s1, -1
141 s_sub_u32 s5, s1, s2
[all …]
H A Dgfx7_asm_sop2.s3 s_add_u32 s5, s1, s2
45 s_add_u32 s5, s103, s2
75 s_add_u32 s5, m0, s2
84 s_add_u32 s5, 0, s2
87 s_add_u32 s5, -1, s2
90 s_add_u32 s5, 0.5, s2
141 s_add_u32 s5, s1, m0
150 s_add_u32 s5, s1, 0
153 s_add_u32 s5, s1, -1
177 s_sub_u32 s5, s1, s2
[all …]
H A Dgfx8_asm_sop2.s3 s_add_u32 s5, s1, s2
45 s_add_u32 s5, s101, s2
75 s_add_u32 s5, m0, s2
84 s_add_u32 s5, 0, s2
87 s_add_u32 s5, -1, s2
90 s_add_u32 s5, 0.5, s2
141 s_add_u32 s5, s1, m0
150 s_add_u32 s5, s1, 0
153 s_add_u32 s5, s1, -1
177 s_sub_u32 s5, s1, s2
[all …]
H A Dgfx8_asm_sop1.s3 s_mov_b32 s5, s1
45 s_mov_b32 s5, s101
75 s_mov_b32 s5, m0
84 s_mov_b32 s5, 0
87 s_mov_b32 s5, -1
90 s_mov_b32 s5, 0.5
93 s_mov_b32 s5, -4.0
189 s_cmov_b32 s5, s1
270 s_cmov_b32 s5, 0
456 s_not_b32 s5, 0
[all …]
H A Dgfx7_asm_sop1.s3 s_mov_b32 s5, s1
45 s_mov_b32 s5, s103
75 s_mov_b32 s5, m0
84 s_mov_b32 s5, 0
87 s_mov_b32 s5, -1
90 s_mov_b32 s5, 0.5
93 s_mov_b32 s5, -4.0
189 s_cmov_b32 s5, s1
270 s_cmov_b32 s5, 0
456 s_not_b32 s5, 0
[all …]
H A Dgfx9_asm_sop1.s3 s_mov_b32 s5, s1
33 s_mov_b32 s5, s101
51 s_mov_b32 s5, m0
60 s_mov_b32 s5, 0
63 s_mov_b32 s5, -1
66 s_mov_b32 s5, 0.5
69 s_mov_b32 s5, -4.0
153 s_cmov_b32 s5, s1
210 s_cmov_b32 s5, 0
360 s_not_b32 s5, 0
[all …]
H A Dgfx9_asm_smem.s3 s_load_dword s5, s[2:3], s0
24 s_load_dword s5, s[4:5], s0
27 s_load_dword s5, s[100:101], s0
33 s_load_dword s5, vcc, s0
39 s_load_dword s5, s[2:3], s101
48 s_load_dword s5, s[2:3], vcc_lo
57 s_load_dword s5, s[2:3], m0
60 s_load_dword s5, s[2:3], 0x0
3096 s_atomic_add s5, vcc, s0
3165 s_atomic_sub s5, vcc, s0
[all …]
H A Dgfx11_asm_smem.s8 s_load_b32 s5, s[2:3], s0
20 s_load_b32 s5, s[4:5], s0
23 s_load_b32 s5, s[100:101], s0
26 s_load_b32 s5, vcc, s0
29 s_load_b32 s5, s[2:3], s101
32 s_load_b32 s5, s[2:3], vcc_lo
35 s_load_b32 s5, s[2:3], vcc_hi
38 s_load_b32 s5, s[2:3], m0
41 s_load_b32 s5, s[2:3], 0x0
47 s_load_b32 s5, s[2:3], s0 glc
[all …]
H A Dsmem.s305 s_atomic_add s5, s[2:3], s101
310 s_atomic_add s5, s[2:3], 0x0
325 s_atomic_and s5, s[2:3], s101
385 s_atomic_or s5, s[2:3], 0x0
395 s_atomic_smax s5, s[2:3], s101
405 s_atomic_smin s5, s[2:3], s101
415 s_atomic_sub s5, s[2:3], s101
425 s_atomic_swap s5, s[2:3], s101
445 s_atomic_umin s5, s[2:3], s101
455 s_atomic_xor s5, s[2:3], s101
[all …]
H A Dgfx10_asm_smem.s8 s_load_dword s5, s[2:3], s0
20 s_load_dword s5, s[4:5], s0
23 s_load_dword s5, s[100:101], s0
26 s_load_dword s5, vcc, s0
29 s_load_dword s5, s[2:3], s101
32 s_load_dword s5, s[2:3], vcc_lo
35 s_load_dword s5, s[2:3], vcc_hi
38 s_load_dword s5, s[2:3], m0
41 s_load_dword s5, s[2:3], null
44 s_load_dword s5, s[2:3], 0x0
[all …]
H A Dsop2.s241 s_lshl1_add_u32 s5, s1, s2
246 s_lshl1_add_u32 s5, -1, s2
251 s_lshl1_add_u32 s5, s1, 0
276 s_lshl3_add_u32 s5, s1, s101
286 s_lshl4_add_u32 s5, -1, s2
291 s_mul_hi_i32 s5, s101, s2
296 s_mul_hi_i32 s5, 0, s2
306 s_mul_hi_i32 s5, s1, s101
311 s_mul_hi_i32 s5, s1, 0
321 s_mul_hi_u32 s5, s1, s101
[all …]
H A Dgfx7_asm_smrd.s3 s_load_dword s5, s[2:3], s2
36 s_load_dword s5, s[4:5], s2
39 s_load_dword s5, s[102:103], s2
45 s_load_dword s5, vcc, s2
48 s_load_dword s5, tba, s2
51 s_load_dword s5, tma, s2
57 s_load_dword s5, s[2:3], s103
66 s_load_dword s5, s[2:3], vcc_lo
69 s_load_dword s5, s[2:3], vcc_hi
72 s_load_dword s5, s[2:3], tba_lo
[all …]
H A Dgfx11_asm_smem_alias.s7 s_load_dword s5, s[2:3], s0
19 s_load_dword s5, s[4:5], s0
22 s_load_dword s5, s[100:101], s0
25 s_load_dword s5, vcc, s0
28 s_load_dword s5, s[2:3], s101
31 s_load_dword s5, s[2:3], vcc_lo
34 s_load_dword s5, s[2:3], vcc_hi
37 s_load_dword s5, s[2:3], m0
40 s_load_dword s5, s[2:3], 0x0
43 s_load_dword s5, s[2:3], s0 glc
[all …]
H A Dgfx8_asm_smem.s3 s_load_dword s5, s[2:3], s2
36 s_load_dword s5, s[4:5], s2
39 s_load_dword s5, s[100:101], s2
45 s_load_dword s5, vcc, s2
48 s_load_dword s5, tba, s2
51 s_load_dword s5, tma, s2
57 s_load_dword s5, s[2:3], s101
66 s_load_dword s5, s[2:3], vcc_lo
69 s_load_dword s5, s[2:3], vcc_hi
72 s_load_dword s5, s[2:3], tba_lo
[all …]
/llvm-project-15.0.7/mlir/include/mlir/Dialect/Linalg/IR/
H A DLinalgNamedStructuredOps.yaml429 shape_map: affine_map<()[s0, s1, s2, s3, s4, s5] -> (s4, s1, s5, s3)>
434 shape_map: affine_map<()[s0, s1, s2, s3, s4, s5] -> (s0, s4, s2, s5)>
1081 shape_map: affine_map<()[s0, s1, s2, s3, s4, s5] -> (s1, s3, s5)>
1149 s5)>
1249 s1, s5, s10)>
1347 s1, s5, s10)>
1454 s1, s5, s10)>
1595 (s5, s9)>
1868 shape_map: affine_map<()[s0, s1, s2, s3, s4, s5] -> (s3, s5)>
1873 shape_map: affine_map<()[s0, s1, s2, s3, s4, s5] -> (s0, s1, s5)>
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dllvm.amdgcn.image.atomic.dim.ll15 ; GFX6-NEXT: s_mov_b32 s3, s5
17 ; GFX6-NEXT: s_mov_b32 s5, s7
29 ; GFX8-NEXT: s_mov_b32 s3, s5
31 ; GFX8-NEXT: s_mov_b32 s5, s7
43 ; GFX900-NEXT: s_mov_b32 s3, s5
45 ; GFX900-NEXT: s_mov_b32 s5, s7
92 ; GFX6-NEXT: s_mov_b32 s3, s5
94 ; GFX6-NEXT: s_mov_b32 s5, s7
106 ; GFX8-NEXT: s_mov_b32 s3, s5
108 ; GFX8-NEXT: s_mov_b32 s5, s7
[all …]
H A Dllvm.amdgcn.image.store.2d.ll13 ; GFX6-NEXT: s_mov_b32 s3, s5
15 ; GFX6-NEXT: s_mov_b32 s5, s7
26 ; GFX8-NEXT: s_mov_b32 s3, s5
28 ; GFX8-NEXT: s_mov_b32 s5, s7
39 ; GFX10-NEXT: s_mov_b32 s3, s5
41 ; GFX10-NEXT: s_mov_b32 s5, s7
52 ; GFX11-NEXT: s_mov_b32 s3, s5
70 ; GFX6-NEXT: s_mov_b32 s3, s5
72 ; GFX6-NEXT: s_mov_b32 s5, s7
83 ; GFX8-NEXT: s_mov_b32 s3, s5
[all …]
H A Dllvm.amdgcn.image.load.1d.ll14 ; GFX68-NEXT: s_mov_b32 s3, s5
16 ; GFX68-NEXT: s_mov_b32 s5, s7
28 ; GFX10-NEXT: s_mov_b32 s3, s5
30 ; GFX10-NEXT: s_mov_b32 s5, s7
42 ; NOPRT-NEXT: s_mov_b32 s3, s5
44 ; NOPRT-NEXT: s_mov_b32 s5, s7
60 ; GFX68-NEXT: s_mov_b32 s3, s5
62 ; GFX68-NEXT: s_mov_b32 s5, s7
74 ; GFX10-NEXT: s_mov_b32 s3, s5
76 ; GFX10-NEXT: s_mov_b32 s5, s7
[all …]
H A Dllvm.amdgcn.image.getresinfo.ll13 ; GFX6-NEXT: s_mov_b32 s3, s5
15 ; GFX6-NEXT: s_mov_b32 s5, s7
27 ; GFX8-NEXT: s_mov_b32 s3, s5
29 ; GFX8-NEXT: s_mov_b32 s5, s7
41 ; GFX10-NEXT: s_mov_b32 s3, s5
43 ; GFX10-NEXT: s_mov_b32 s5, s7
60 ; GFX6-NEXT: s_mov_b32 s3, s5
62 ; GFX6-NEXT: s_mov_b32 s5, s7
74 ; GFX8-NEXT: s_mov_b32 s3, s5
76 ; GFX8-NEXT: s_mov_b32 s5, s7
[all …]
H A Dllvm.amdgcn.image.load.1d.d16.ll42 ; GFX9-NEXT: s_mov_b32 s3, s5
44 ; GFX9-NEXT: s_mov_b32 s5, s7
102 ; GFX9-NEXT: s_mov_b32 s3, s5
104 ; GFX9-NEXT: s_mov_b32 s5, s7
162 ; GFX9-NEXT: s_mov_b32 s3, s5
164 ; GFX9-NEXT: s_mov_b32 s5, s7
222 ; GFX9-NEXT: s_mov_b32 s3, s5
224 ; GFX9-NEXT: s_mov_b32 s5, s7
285 ; GFX9-NEXT: s_mov_b32 s3, s5
287 ; GFX9-NEXT: s_mov_b32 s5, s7
[all …]
H A Dllvm.amdgcn.image.atomic.dim.a16.ll12 ; GFX9-NEXT: s_mov_b32 s3, s5
14 ; GFX9-NEXT: s_mov_b32 s5, s7
26 ; GFX10-NEXT: s_mov_b32 s3, s5
28 ; GFX10-NEXT: s_mov_b32 s5, s7
46 ; GFX9-NEXT: s_mov_b32 s3, s5
48 ; GFX9-NEXT: s_mov_b32 s5, s7
60 ; GFX10-NEXT: s_mov_b32 s3, s5
62 ; GFX10-NEXT: s_mov_b32 s5, s7
80 ; GFX9-NEXT: s_mov_b32 s3, s5
82 ; GFX9-NEXT: s_mov_b32 s5, s7
[all …]
/llvm-project-15.0.7/libcxx/test/std/strings/basic.string/string.contains/
H A Dcontains.string_view.pass.cpp28 S s5 {s , 5}; in test() local
66 assert( s5.contains(sv0)); in test()
67 assert( s5.contains(sv1)); in test()
68 assert( s5.contains(sv2)); in test()
69 assert( s5.contains(sv3)); in test()
70 assert( s5.contains(sv4)); in test()
71 assert( s5.contains(sv5)); in test()
72 assert(!s5.contains(svNot)); in test()
73 assert(!s5.contains(svNot2)); in test()
74 assert(!s5.contains(svNot3)); in test()
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AMDGPU/
H A Dsop2_gfx9.txt3 # GFX9: s_lshl1_add_u32 s5, 0, s2 ; encoding: [0x80,0x02,0x05,0x97]
6 # GFX9: s_lshl2_add_u32 s5, 0xaf123456, s2 ; encoding: [0xff,0x02,0x85,0x97,0x56,0x34,0x12,0xaf]
9 # GFX9: s_lshl3_add_u32 s5, s1, -1 ; encoding: [0x01,0xc1,0x05,0x98]
12 # GFX9: s_lshl4_add_u32 s5, s1, 0xaf123456 ; encoding: [0x01,0xff,0x85,0x98,0x56,0x34,0x12,0xaf]
15 # GFX9: s_mul_hi_i32 s5, s101, s2 ; encoding: [0x65,0x02,0x85,0x96]
18 # GFX9: s_mul_hi_i32 s5, 0, s2 ; encoding: [0x80,0x02,0x85,0x96]
21 # GFX9: s_mul_hi_i32 s5, 0xaf123456, s2 ; encoding: [0xff,0x02,0x85,0x96,0x56,0x34,0x12,0xaf]
24 # GFX9: s_mul_hi_u32 s5, s1, -1 ; encoding: [0x01,0xc1,0x05,0x96]
27 # GFX9: s_mul_hi_u32 s5, s1, 0xaf123456 ; encoding: [0x01,0xff,0x05,0x96,0x56,0x34,0x12,0xaf]
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Drv32a-valid.s58 amomax.w s7, s6, (s5)
61 amominu.w s6, s5, (s4)
64 amomaxu.w s5, s4, (s3)
86 amomax.w.aq s7, s6, (s5)
89 amominu.w.aq s6, s5, (s4)
92 amomaxu.w.aq s5, s4, (s3)
114 amomax.w.rl s7, s6, (s5)
117 amominu.w.rl s6, s5, (s4)
120 amomaxu.w.rl s5, s4, (s3)
142 amomax.w.aqrl s7, s6, (s5)
[all …]
/llvm-project-15.0.7/clang/test/Analysis/
H A Dctor-array.cpp114 struct s5 { struct
118 s5() : x(c++) {} in s5() argument
132 s5::c = 0; in g1()
133 s5 *arr = new s5[4]; in g1()
134 new (arr + 1) s5[3]; in g1()
143 s5::c = 0; in g2()
144 s5 arr[4]; in g2()
153 s5::c = 0; in g3()
154 s5 arr[2][2]; in g3()
163 s5::c = 0; in h1()
[all …]

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