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Searched refs:s41 (Results 1 – 25 of 25) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-abi-varargs.ll205 %struct.s41 = type { i32, i16, i32, i16 }
224 %vs = alloca %struct.s41, align 16
237 %4 = bitcast i8* %ap.align to %struct.s41*
238 %5 = bitcast %struct.s41* %vs to i8*
239 %6 = bitcast %struct.s41* %4 to i8*
245 define void @bar2(i32 %x, i128 %s41.coerce) nounwind {
266 %s41 = alloca %struct.s41, align 16
268 %0 = bitcast %struct.s41* %s41 to i128*
269 store i128 %s41.coerce, i128* %0, align 1
271 %2 = bitcast %struct.s41* %s41 to i128*
H A Darm64-abi_align.ll15 %struct.s41 = type { i32, i16, i32, i16 }
26 @g41 = common global %struct.s41 zeroinitializer, align 16
27 @g41_2 = common global %struct.s41 zeroinitializer, align 16
224 %0 = load i128, i128* bitcast (%struct.s41* @g41 to i128*), align 16
225 %1 = load i128, i128* bitcast (%struct.s41* @g41_2 to i128*), align 16
242 %0 = load i128, i128* bitcast (%struct.s41* @g41 to i128*), align 16
243 %1 = load i128, i128* bitcast (%struct.s41* @g41_2 to i128*), align 16
495 %0 = load i128, i128* bitcast (%struct.s41* @g41 to i128*), align 16
516 %0 = load i64, i64* bitcast (%struct.s41* @g41 to i64*), align 16
/llvm-project-15.0.7/llvm/test/MC/Hexagon/
H A Dsysregs.s32 r1:0=s41:40
33 # CHECK: r1:0 = s41:40
H A Dsysregs2.s28 r1:0 =s41:40
29 # CHECK: { r1:0 = s41:40 }
/llvm-project-15.0.7/clang/test/Sema/
H A Dbitfield-layout_1.c55 } s41; variable
56 CHECK_SIZE(s41,12)
H A Dtest-wunaligned-access.c503 struct U41 s41; variable
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dspill_more_than_wavesize_csr_sgprs.ll12 "~{s35},~{s36},~{s37},~{s38},~{s39},~{s40},~{s41},~{s42}
34 "~{s35},~{s36},~{s37},~{s38},~{s39},~{s40},~{s41},~{s42}
H A Dindirect-call.ll411 ; GCN-NEXT: v_writelane_b32 v40, s41, 9
457 ; GCN-NEXT: v_readlane_b32 s41, v40, 9
579 ; GCN-NEXT: v_writelane_b32 v40, s41, 9
628 ; GCN-NEXT: v_readlane_b32 s41, v40, 9
751 ; GCN-NEXT: v_writelane_b32 v40, s41, 9
799 ; GCN-NEXT: v_readlane_b32 s41, v40, 9
981 ; GCN-NEXT: v_readlane_b32 s41, v40, 9
1179 ; GCN-NEXT: v_readlane_b32 s41, v40, 9
1374 ; GCN-NEXT: v_readlane_b32 s41, v40, 9
1577 ; GCN-NEXT: v_readlane_b32 s41, v40, 9
[all …]
H A Ddwarf-multi-register-use-crash.ll32 ; CHECK-NEXT: v_writelane_b32 v40, s41, 9
83 ; CHECK-NEXT: v_readlane_b32 s41, v40, 9
H A Dcallee-frame-setup.ll300 "~{s40},~{s41},~{s42},~{s43},~{s44},~{s45},~{s46},~{s47},~{s48},~{s49}
349 "~{s39},~{s40},~{s41},~{s42},~{s43},~{s44},~{s45},~{s46},~{s47},~{s48},~{s49}
600 ,~{s40},~{s41},~{s42},~{s43},~{s44},~{s45},~{s46},~{s47},~{s48},~{s49}
635 ,~{s40},~{s41},~{s42},~{s43},~{s44},~{s45},~{s46},~{s47},~{s48},~{s49}
672 ,~{s40},~{s41},~{s42},~{s43},~{s44},~{s45},~{s46},~{s47},~{s48},~{s49}
H A Dbranch-relax-spill.ll138 ; CHECK-NEXT: s_mov_b32 s41, 0
479 ; CHECK-NEXT: ; reg use s41
710 %sgpr41 = tail call i32 asm sideeffect "s_mov_b32 s41, 0", "={s41}"() #0
831 tail call void asm sideeffect "; reg use $0", "{s41}"(i32 %sgpr41) #0
916 ; CHECK-NEXT: v_writelane_b32 v0, s41, 10
1104 ; CHECK-NEXT: s_mov_b32 s41, 0
1445 ; CHECK-NEXT: ; reg use s41
1693 ; CHECK-NEXT: v_readlane_b32 s41, v0, 10
1753 %sgpr41 = tail call i32 asm sideeffect "s_mov_b32 s41, 0", "={s41}"() #0
1874 tail call void asm sideeffect "; reg use $0", "{s41}"(i32 %sgpr41) #0
H A Dstack-realign.ll274 ,~{s40},~{s41},~{s42},~{s43},~{s44},~{s45},~{s46},~{s47},~{s48},~{s49}
315 ,~{s40},~{s41},~{s42},~{s43},~{s44},~{s45},~{s46},~{s47},~{s48},~{s49}
H A Dwwm-reserved-spill.ll148 ; GFX9-O0-NEXT: v_writelane_b32 v5, s41, 1
720 ; GFX9-O0-NEXT: s_mov_b32 s41, s35
725 ; GFX9-O0-NEXT: v_mov_b32_e32 v2, s41
737 ; GFX9-O0-NEXT: v_mov_b32_e32 v2, s41
746 ; GFX9-O0-NEXT: v_mov_b32_e32 v2, s41
H A Dpartial-sgpr-to-vgpr-spills.ll236 ; GCN-NEXT: v_readlane_b32 s41, v1, 37
558 ; GCN-NEXT: v_readlane_b32 s41, v0, 37
783 ; GCN-NEXT: v_readlane_b32 s41, v31, 37
1018 ; GCN-NEXT: v_readlane_b32 s41, v31, 37
H A Dpromote-constOffset-to-imm.ll2034 ; GFX8-NEXT: s_mov_b32 s41, SCRATCH_RSRC_DWORD1
2038 ; GFX8-NEXT: s_addc_u32 s41, s41, 0
2103 ; GFX9-NEXT: s_mov_b32 s41, SCRATCH_RSRC_DWORD1
2107 ; GFX9-NEXT: s_addc_u32 s41, s41, 0
2162 ; GFX10-NEXT: s_mov_b32 s41, SCRATCH_RSRC_DWORD1
2166 ; GFX10-NEXT: s_addc_u32 s41, s41, 0
H A Dload-constant-i16.ll2927 ; GCN-NOHSA-SI-NEXT: s_and_b32 s41, s41, 0xffff
3067 ; GCN-HSA-NEXT: s_lshr_b32 s57, s41, 16
3083 ; GCN-HSA-NEXT: s_and_b32 s41, s41, 0xffff
3160 ; GCN-HSA-NEXT: v_mov_b32_e32 v22, s41
3386 ; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s41
3795 ; GCN-HSA-NEXT: s_ashr_i32 s57, s41, 16
3865 ; GCN-HSA-NEXT: s_sext_i32_i16 s41, s41
3894 ; GCN-HSA-NEXT: v_mov_b32_e32 v22, s41
6798 ; GCN-HSA-NEXT: v_mov_b32_e32 v23, s41
6799 ; GCN-HSA-NEXT: s_addc_u32 s41, s17, 0
[all …]
H A Dunstructured-cfg-def-use-issue.ll206 ; GCN-NEXT: v_writelane_b32 v40, s41, 9
H A Dinsert_vector_dynelt.ll213 ; GCN-NEXT: v_mov_b32_e32 v5, s41
804 ; GCN-NEXT: v_mov_b32_e32 v5, s41
1077 ; GCN-NEXT: s_lshr_b32 s41, s7, 21
1092 ; GCN-NEXT: v_mov_b32_e32 v17, s41
H A Dgfx-callable-argument-types.ll6321 ; GFX9-NEXT: v_writelane_b32 v40, s41, 9
6375 ; GFX9-NEXT: v_readlane_b32 s41, v40, 9
6470 ; GFX10-NEXT: v_readlane_b32 s41, v40, 9
6562 ; GFX11-NEXT: v_readlane_b32 s41, v40, 9
12010 ; GFX9-NEXT: s_mov_b32 s25, s41
12108 ; GFX10-NEXT: s_mov_b32 s25, s41
12214 ; GFX11-NEXT: s_mov_b32 s25, s41
12319 ; GFX10-SCRATCH-NEXT: s_mov_b32 s25, s41
12438 ; GFX9-NEXT: s_mov_b32 s25, s41
12541 ; GFX10-NEXT: s_mov_b32 s25, s41
[all …]
H A Dds_read2.ll1353 ; CI-NEXT: s_addc_u32 s41, s41, 0
/llvm-project-15.0.7/clang/test/CXX/lex/lex.charset/
H A Dp2-cxx98.cpp41 const char *s41 = "\u0041"; // A, expected-error {{character 'A' cannot be specified by a universal… variable
/llvm-project-15.0.7/clang/test/CodeGen/
H A Darm64-arguments.c472 struct s41 struct
479 typedef struct s41 s41_with_align; argument
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dinsertelement-stack-lower.ll25 ; GCN-NEXT: v_mov_b32_e32 v5, s41
128 ; GCN-NEXT: v_mov_b32_e32 v0, s41
H A Dextractelement.ll2056 ; GCN-NEXT: s_mov_b32 s41, 0x40c00000
2095 ; GFX10PLUS-NEXT: s_mov_b32 s41, 0x40c00000
2138 ; GCN-NEXT: s_mov_b32 s41, 0x40080000
2173 ; GFX10PLUS-NEXT: s_mov_b32 s41, 0x40080000
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td330 def ISDBMBXOUT: Rs<41, "isdbmbxout", ["s41"]>, DwarfRegNum<[185]>;
394 def S41_40 : Rss<40, "s41:40", [ISDBMBXIN, ISDBMBXOUT]>, DwarfRegNum<[184]>;