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/llvm-project-15.0.7/llvm/test/MC/AMDGPU/
H A Dgfx10_asm_sop.s8 s_mov_b32 s0, s1
14 s_mov_b32 s0, s104
47 s_mov_b32 s0, m0
50 s_mov_b32 s0, 0
53 s_mov_b32 s0, -1
56 s_mov_b32 s0, 0.5
59 s_mov_b32 s0, -4.0
110 s_cmov_b32 s0, s1
152 s_cmov_b32 s0, 0
254 s_not_b32 s0, 0
[all …]
H A Dgfx11_asm_scalar.s3 s_mov_b32 s0, s1
9 s_mov_b32 s0, s104
42 s_mov_b32 s0, m0
45 s_mov_b32 s0, 0
48 s_mov_b32 s0, -1
51 s_mov_b32 s0, 0.5
54 s_mov_b32 s0, -4.0
63 s_mov_b32 s0, null
159 s_cmov_b32 s0, 0
261 s_not_b32 s0, 0
[all …]
H A Dgfx9_asm_smem.s3 s_load_dword s5, s[2:3], s0
6 s_load_dword s101, s[2:3], s0
15 s_load_dword vcc_lo, s[2:3], s0
18 s_load_dword vcc_hi, s[2:3], s0
21 s_load_dword ttmp15, s[2:3], s0
24 s_load_dword s5, s[4:5], s0
27 s_load_dword s5, s[100:101], s0
33 s_load_dword s5, vcc, s0
1341 s_atc_probe 0x0, vcc, s0
1431 s_dcache_discard vcc, s0
[all …]
H A Dgfx11_asm_smem_alias.s7 s_load_dword s5, s[2:3], s0
10 s_load_dword s101, s[2:3], s0
13 s_load_dword vcc_lo, s[2:3], s0
16 s_load_dword vcc_hi, s[2:3], s0
19 s_load_dword s5, s[4:5], s0
22 s_load_dword s5, s[100:101], s0
25 s_load_dword s5, vcc, s0
43 s_load_dword s5, s[2:3], s0 glc
46 s_load_dword s5, s[2:3], s0 dlc
64 s_load_dwordx2 vcc, s[2:3], s0
[all …]
H A Dmtbuf-gfx10.s114 tbuffer_store_format_x v0, v1, s[0:3] format:0 s0 idxen
117 tbuffer_store_format_x v0, v1, s[0:3] format:1 s0 idxen
123 tbuffer_load_format_d16_x v0, off, s[0:3] s0
127 tbuffer_store_format_x v0, v1, s[0:3] format:0 s0 idxen
130 tbuffer_store_format_x v0, v1, s[0:3] format:0 s0 idxen
140 tbuffer_load_format_d16_x v0, off, s[0:3], format:128, s0
152 tbuffer_load_format_d16_x v0, off, s[0:3], format:1,, s0
155 tbuffer_load_format_d16_x v0, off, s[0:3], format:1:, s0
158 tbuffer_load_format_d16_x v0, off, s[0:3],, format:1, s0
165 tbuffer_store_format_xyzw v[1:4], v1, s[4:7], s0 format:0 idxen
[all …]
H A Dgfx10_asm_smem.s8 s_load_dword s5, s[2:3], s0
11 s_load_dword s101, s[2:3], s0
14 s_load_dword vcc_lo, s[2:3], s0
17 s_load_dword vcc_hi, s[2:3], s0
20 s_load_dword s5, s[4:5], s0
23 s_load_dword s5, s[100:101], s0
26 s_load_dword s5, vcc, s0
50 s_load_dword s5, s[2:3], s0 glc
53 s_load_dword s5, s[2:3], s0 dlc
74 s_load_dwordx2 vcc, s[2:3], s0
[all …]
H A Dgfx11_asm_smem.s8 s_load_b32 s5, s[2:3], s0
11 s_load_b32 s101, s[2:3], s0
14 s_load_b32 vcc_lo, s[2:3], s0
17 s_load_b32 vcc_hi, s[2:3], s0
20 s_load_b32 s5, s[4:5], s0
23 s_load_b32 s5, s[100:101], s0
26 s_load_b32 s5, vcc, s0
47 s_load_b32 s5, s[2:3], s0 glc
50 s_load_b32 s5, s[2:3], s0 dlc
68 s_load_b64 vcc, s[2:3], s0
[all …]
H A Dmtbuf.s96 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7] dfmt:-1 nfmt:1 s0
99 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7] dfmt:16 nfmt:1 s0
102 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7] dfmt:1 nfmt:-1 s0
105 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7] dfmt:1 nfmt:8 s0
120 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7] dfmt:1 dfmt:1 s0
123 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7] nfmt:1 nfmt:1 s0
143 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:0
148 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:127
303 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:-1
307 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:128
[all …]
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Ddirective-arch_extension-fp.s22 vselgt.f32 s0, s0, s0
24 vselge.f32 s0, s0, s0
26 vseleq.f32 s0, s0, s0
28 vselvs.f32 s0, s0, s0
30 vmaxnm.f32 s0, s0, s0
32 vminnm.f32 s0, s0, s0
158 vselgt.f32 s0, s0, s0
160 vselge.f32 s0, s0, s0
162 vseleq.f32 s0, s0, s0
164 vselvs.f32 s0, s0, s0
[all …]
H A Dfullfp16.s6 vadd.f16 s0, s1, s0
10 vsub.f16 s0, s1, s0
14 vdiv.f16 s0, s1, s0
18 vmul.f16 s0, s1, s0
58 vabs.f16 s0, s0
62 vneg.f16 s0, s0
66 vsqrt.f16 s0, s0
70 vcvt.f16.s32 s0, s0
71 vcvt.f16.u32 s0, s0
151 vselgt.f16 s0, s1, s0
[all …]
H A Ddirective-arch_extension-simd.s19 vmaxnm.f32 s0, s0, s0
21 vminnm.f32 s0, s0, s0
29 vcvta.s32.f32 s0, s0
31 vcvta.u32.f32 s0, s0
37 vcvtn.s32.f32 s0, s0
39 vcvtn.u32.f32 s0, s0
87 vrinta.f32 s0, s0
95 vrintn.f32 s0, s0
103 vrintp.f32 s0, s0
127 vmaxnm.f32 s0, s0, s0
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/VE/Scalar/
H A Dctlz.ll14 ; CHECK-NEXT: ldz %s0, %s0
15 ; CHECK-NEXT: lea %s0, 64(, %s0)
26 ; CHECK-NEXT: ldz %s0, %s0
36 ; CHECK-NEXT: ldz %s0, %s0
47 ; CHECK-NEXT: ldz %s0, %s0
59 ; CHECK-NEXT: ldz %s0, %s0
71 ; CHECK-NEXT: ldz %s0, %s0
84 ; CHECK-NEXT: ldz %s0, %s0
96 ; CHECK-NEXT: ldz %s0, %s0
183 ; CHECK-NEXT: ldz %s0, %s0
[all …]
H A Dbr_jt.ll13 ; CHECK-NEXT: and %s0, %s0, (32)0
35 ; PIC-NEXT: and %s0, %s0, (32)0
78 ; CHECK-NEXT: and %s0, %s0, (32)0
84 ; CHECK-NEXT: sll %s0, %s0, 2
98 ; PIC-NEXT: and %s0, %s0, (32)0
108 ; PIC-NEXT: sll %s0, %s0, 2
154 ; CHECK-NEXT: sll %s0, %s0, 2
185 ; PIC-NEXT: sll %s0, %s0, 2
235 ; CHECK-NEXT: sll %s0, %s0, 2
266 ; PIC-NEXT: sll %s0, %s0, 2
[all …]
H A Dselect_cc.ll12 ; CHECK-NEXT: xor %s0, %s0, %s1
25 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
38 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
103 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
130 ; CHECK-NEXT: xor %s0, %s0, %s2
131 ; CHECK-NEXT: or %s0, %s0, %s1
146 ; CHECK-NEXT: xor %s0, %s0, %s2
147 ; CHECK-NEXT: or %s0, %s0, %s1
200 ; CHECK-NEXT: xor %s0, %s0, %s1
319 ; CHECK-NEXT: or %s0, %s0, %s1
[all …]
H A Dsubtraction.ll6 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
7 ; CHECK-NEXT: sll %s0, %s0, 56
8 ; CHECK-NEXT: sra.l %s0, %s0, 56
17 ; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
18 ; CHECK-NEXT: sll %s0, %s0, 48
19 ; CHECK-NEXT: sra.l %s0, %s0, 48
38 ; CHECK-NEXT: subs.l %s0, %s0, %s1
53 ; CHECK-NEXT: subs.l %s0, %s0, %s2
63 ; CHECK-NEXT: and %s0, %s0, (56)0
117 ; CHECK-NEXT: sll %s0, %s0, 56
[all …]
H A Daddition.ll6 ; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
7 ; CHECK-NEXT: sll %s0, %s0, 56
8 ; CHECK-NEXT: sra.l %s0, %s0, 56
17 ; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
18 ; CHECK-NEXT: sll %s0, %s0, 48
19 ; CHECK-NEXT: sra.l %s0, %s0, 48
38 ; CHECK-NEXT: adds.l %s0, %s1, %s0
48 ; CHECK-NEXT: adds.l %s0, %s2, %s0
63 ; CHECK-NEXT: and %s0, %s0, (56)0
117 ; CHECK-NEXT: sll %s0, %s0, 56
[all …]
H A Dload_off.ll17 ; CHECK-NEXT: and %s0, %s0, (32)0
19 ; CHECK-NEXT: ld1b.sx %s0, 2(, %s0)
31 ; CHECK-NEXT: and %s0, %s0, (32)0
33 ; CHECK-NEXT: ld2b.sx %s0, 4(, %s0)
45 ; CHECK-NEXT: and %s0, %s0, (32)0
47 ; CHECK-NEXT: ldl.sx %s0, 8(, %s0)
59 ; CHECK-NEXT: and %s0, %s0, (32)0
61 ; CHECK-NEXT: ld %s0, 16(, %s0)
73 ; CHECK-NEXT: and %s0, %s0, (32)0
132 ; CHECK-NEXT: ld %s0, 16(, %s0)
[all …]
H A Dright_shift.ll6 ; CHECK-NEXT: sra.w.sx %s0, %s0, %s1
7 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
19 ; CHECK-NEXT: sra.w.sx %s0, %s0, %s1
41 ; CHECK-NEXT: sra.l %s0, %s0, %s1
50 ; CHECK-NEXT: and %s0, %s0, (32)0
51 ; CHECK-NEXT: srl %s0, %s0, %s1
65 ; CHECK-NEXT: srl %s0, %s0, %s1
79 ; CHECK-NEXT: srl %s0, %s0, %s1
136 ; CHECK-NEXT: srl %s0, %s0, 5
147 ; CHECK-NEXT: srl %s0, %s0, 5
[all …]
H A Dload_gv.ll17 ; CHECK-NEXT: and %s0, %s0, (32)0
31 ; CHECK-NEXT: and %s0, %s0, (32)0
33 ; CHECK-NEXT: ld %s0, (, %s0)
44 ; CHECK-NEXT: and %s0, %s0, (32)0
46 ; CHECK-NEXT: ldu %s0, (, %s0)
57 ; CHECK-NEXT: and %s0, %s0, (32)0
71 ; CHECK-NEXT: and %s0, %s0, (32)0
73 ; CHECK-NEXT: ld %s0, (, %s0)
84 ; CHECK-NEXT: and %s0, %s0, (32)0
86 ; CHECK-NEXT: ldl.sx %s0, (, %s0)
[all …]
H A Dleft_shift.ll6 ; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
7 ; CHECK-NEXT: sll %s0, %s0, 56
8 ; CHECK-NEXT: sra.l %s0, %s0, 56
20 ; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
21 ; CHECK-NEXT: sll %s0, %s0, 48
22 ; CHECK-NEXT: sra.l %s0, %s0, 48
43 ; CHECK-NEXT: sll %s0, %s0, %s1
87 ; CHECK-NEXT: sll %s0, %s0, %s1
97 ; CHECK-NEXT: sll %s0, %s0, 56
108 ; CHECK-NEXT: sll %s0, %s0, 48
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/VE/Vector/
H A Dvec_broadcast.ll9 ; CHECK-NEXT: vbrd %v0, %s0
19 ; CHECK-NEXT: lea %s0, 256
20 ; CHECK-NEXT: lvl %s0
44 ; CHECK-NEXT: lvl %s0
55 ; CHECK-NEXT: and %s0, %s0, (32)0
69 ; CHECK-NEXT: lvl %s0
93 ; CHECK-NEXT: lvl %s0
130 ; CHECK-NEXT: and %s0, %s0, (32)0
144 ; CHECK-NEXT: lvl %s0
168 ; CHECK-NEXT: lvl %s0
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dmve-vecreduce-fmul.ll8 ; CHECK-NEXT: vmul.f32 s0, s0, s1
9 ; CHECK-NEXT: vmul.f32 s0, s4, s0
20 ; CHECK-FP-NEXT: vmul.f32 s0, s0, s1
21 ; CHECK-FP-NEXT: vmul.f32 s0, s0, s2
22 ; CHECK-FP-NEXT: vmul.f32 s0, s4, s0
67 ; CHECK-NEXT: vmul.f16 s0, s0, s2
68 ; CHECK-NEXT: vmul.f16 s0, s4, s0
254 ; CHECK-NEXT: vmovx.f16 s0, s0
266 ; CHECK-NEXT: vmovx.f16 s0, s0
281 ; CHECK-NEXT: vmovx.f16 s0, s0
[all …]
H A Dmve-vecreduce-fadd.ll8 ; CHECK-NEXT: vadd.f32 s0, s0, s1
9 ; CHECK-NEXT: vadd.f32 s0, s4, s0
20 ; CHECK-FP-NEXT: vadd.f32 s0, s0, s1
21 ; CHECK-FP-NEXT: vadd.f32 s0, s0, s2
22 ; CHECK-FP-NEXT: vadd.f32 s0, s4, s0
42 ; CHECK-FP-NEXT: vadd.f32 s0, s0, s1
67 ; CHECK-NEXT: vadd.f16 s0, s0, s2
68 ; CHECK-NEXT: vadd.f16 s0, s4, s0
254 ; CHECK-NEXT: vmovx.f16 s0, s0
269 ; CHECK-NEXT: vmovx.f16 s0, s0
[all …]
H A Dmve-vecreduce-fminmax.ll8 ; CHECK-NEXT: vminnm.f32 s0, s0, s1
19 ; CHECK-FP-NEXT: vminnm.f32 s0, s0, s1
20 ; CHECK-FP-NEXT: vminnm.f32 s0, s0, s2
25 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s1
26 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s2
27 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s3
40 ; CHECK-FP-NEXT: vminnm.f32 s0, s0, s1
41 ; CHECK-FP-NEXT: vminnm.f32 s0, s0, s2
73 ; CHECK-FP-NEXT: vminnm.f16 s0, s0, s4
74 ; CHECK-FP-NEXT: vminnm.f16 s0, s0, s2
[all …]
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Dcompress-rv32i.s81 srli s0, s0, 31
87 srai s0, s0, 31
93 andi s0, s0, 31
99 sub s0, s0, a5
105 xor s0, s0, a5
111 xor s0, a5, s0
117 or s0, s0, a5
123 or s0, s1, s0
129 and s0, s0, a5
135 and s0, a5, s0
[all …]

12345678910>>...103