| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | Mips16InstrFormats.td | 139 bits<3> ry; 146 let Inst{7-5} = ry; 236 bits<3> ry; 243 let Inst{7-5} = ry; 256 bits<3> ry; 278 bits<3> ry; 300 bits<3> ry; 340 bits<4> ry; 513 bits<3> ry; 537 bits<3> ry; [all …]
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| H A D | Mips16InstrInfo.td | 578 // Format: AND rx, ry MIPS16e 690 // Format: CMP rx, ry MIPS16e 718 // Format: DIV rx, ry MIPS16e 727 // Format: DIVU rx, ry MIPS16e 911 // Format: MULT rx, ry MIPS16e 933 // Format: NEG rx, ry MIPS16e 940 // Format: NOT rx, ry MIPS16e 947 // Format: OR rx, ry MIPS16e 1155 // Format: SLLV ry, rx MIPS16e 1208 // Format: SLT rx, ry MIPS16e [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrFormats16Instr.td | 28 (outs mGPR:$rz), (ins mGPR:$rx, mGPR:$ry), !strconcat(opstr, "\t$rz, $rx, $ry"), 29 [(set mGPR:$rz, (opnode mGPR:$rx, mGPR:$ry)) ]> { 32 bits<3> ry; 36 let Inst{4 - 2} = ry; 105 AddrModeNone, (outs CARRY:$ca), (ins sGPR:$rx, sGPR:$ry), !strconcat(opstr, "\t$rx, $ry"), 107 bits<4> ry; 111 let Inst{9 - 6} = ry;
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| H A D | CSKYInstrFormats.td | 393 let Inst{25 - 21} = regs{9 - 5}; // ry 521 bits<5> ry; 524 let Inst{25 - 21} = ry; 533 // Input: GPR:rx, GPR:ry 534 // Asm string: op rz, rx, ry 539 (ins GPR:$rx, GPR:$ry), op, [(set GPR:$rz, (opnode GPR:$rx, GPR:$ry))]> { 551 bits<5> ry; 554 let Inst{25 - 21} = ry; // ry; 586 (ins GPR:$rx, GPR:$ry), 588 bits<5> ry; [all …]
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| H A D | CSKYInstrFormatsF1.td | 186 bits<5> ry; 190 let Inst{25 - 21} = ry; // ry; 207 : F_XYZ_MEM<sop, sop_su, (outs regtype:$vrz), (ins GPR:$rx, GPR:$ry, uimm2:$imm), 208 op#op_su#"\t$vrz, ($rx, $ry << ${imm})", []>; 217 : F_XYZ_MEM<sop, sop_su, (outs), (ins regtype:$vrz, GPR:$rx, GPR:$ry, uimm2:$imm), 218 op#op_su#"\t$vrz, ($rx, $ry << ${imm})", []>;
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| H A D | CSKYInstrFormatsF2.td | 162 op#"\t$rz, ($rx, $ry << ${imm})", []> { 164 bits<5> ry; 168 let Inst{25-21} = ry;
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| H A D | CSKYInstrInfo.td | 550 (ins GPR:$rx, GPR:$ry, CARRY:$cin), "addc32", []>; 552 (ins GPR:$rx, GPR:$ry, CARRY:$cin), "subc32", []>; 588 (ins GPR:$rx, GPR:$ry), "mul.s32", []>; 590 (ins GPR:$rx, GPR:$ry), "mul.u32", []>; 594 (ins GPRPair:$rz, GPR:$rx, GPR:$ry), "mula.s32", []>; 596 (ins GPRPair:$rz, GPR:$rx, GPR:$ry), "mula.u32", []>; 601 (ins GPR:$rx, GPR:$ry), "mulsh32", []>; 692 let Inst{20 - 16} = 0; //ry 701 let Inst{20 - 16} = 0; //ry
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| H A D | CSKYInstrInfo16Instr.td | 61 let Pattern = [(set mGPR:$rz, (sub mGPR:$rx, mGPR:$ry))] in 320 def TST16 : CSKY16Inst<AddrModeNone, (outs CARRY:$ca), (ins sGPR:$rx, sGPR:$ry), 321 "tst16\t$rx, $ry", []> { 322 bits<4> ry; 326 let Inst{9 - 6} = ry;
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| H A D | CSKYInstrInfoF2.td | 93 def FLDR_S : F2_LDSTR_S<0b0, "fldr", (outs FPR32Op:$rz), (ins GPR:$rx, GPR:$ry, uimm2:$imm)>; 95 def FLDR_D : F2_LDSTR_D<0b0, "fldr", (outs FPR64Op:$rz), (ins GPR:$rx, GPR:$ry, uimm2:$imm)>; 98 def FSTR_S : F2_LDSTR_S<0b1, "fstr", (outs), (ins FPR32Op:$rz, GPR:$rx, GPR:$ry, uimm2:$imm)>; 100 def FSTR_D : F2_LDSTR_D<0b1, "fstr", (outs), (ins FPR64Op:$rz, GPR:$rx, GPR:$ry, uimm2:$imm)>;
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| /llvm-project-15.0.7/flang/lib/Evaluate/ |
| H A D | tools.cpp | 126 ConvertTo(ry, std::move(ix)), std::move(ry))}; in ConvertRealOperands() 136 std::move(rx), std::move(ry))}; in ConvertRealOperands() 162 ConvertTo(ry, std::move(bx)), std::move(ry))}; in ConvertRealOperands() 377 [](Expr<SomeReal> &&rx, Expr<SomeReal> &&ry) { in NumericOperation() argument 379 std::move(rx), std::move(ry))); in NumericOperation() 385 [](Expr<SomeInteger> &&ix, Expr<SomeReal> &&ry) { in NumericOperation() argument 393 std::move(ry.u))); in NumericOperation() 404 [&](Expr<SomeComplex> &&zx, Expr<SomeReal> &&ry) { in NumericOperation() argument 422 [&](BOZLiteralConstant &&bx, Expr<SomeReal> &&ry) { in NumericOperation() argument 535 [&](Expr<SomeInteger> &&ix, Expr<SomeReal> &&ry) { in Relate() argument [all …]
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| /llvm-project-15.0.7/lldb/test/Shell/SymbolFile/NativePDB/Inputs/ |
| H A D | function-types-builtins.lldbinit | 55 dv ry
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| /llvm-project-15.0.7/lldb/test/Shell/SymbolFile/NativePDB/ |
| H A D | function-types-builtins.cpp | 173 auto ry = &unaryret<const volatile int*, 23>; variable
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| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | PBQP-chain.ll | 23 define void @fir(double* nocapture %rx, double* nocapture %ry, double* nocapture %c, double* nocapt… 101 store double %add8.7, double* %ry, align 8
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| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VEInstrFormats.td | 103 bits<2> ry = 0; 106 let sy{1-0} = ry;
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| H A D | VEInstrInfo.td | 1555 let ry = 3, DecoderMethod = "DecodeLoadASI64" in 1557 let ry = 2, DecoderMethod = "DecodeLoadASI64" in 1559 let ry = 1, DecoderMethod = "DecodeLoadASI64" in 1561 let ry = 0, DecoderMethod = "DecodeLoadASI64" in 1565 let ry = 3, DecoderMethod = "DecodeStoreASI64" in 1567 let ry = 2, DecoderMethod = "DecodeStoreASI64" in 1569 let ry = 1, DecoderMethod = "DecodeStoreASI64" in 1571 let ry = 0, DecoderMethod = "DecodeStoreASI64" in
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| /llvm-project-15.0.7/flang/lib/Optimizer/CodeGen/ |
| H A D | CodeGen.cpp | 3195 auto ry = rewriter.create<LLVMOP>(loc, eleTy, y0, y1); in complexSum() local 3198 return rewriter.create<mlir::LLVM::InsertValueOp>(loc, ty, r1, ry, c1); in complexSum()
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