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/llvm-project-15.0.7/clang/test/CodeGen/RISCV/rvb-intrinsics/
H A Driscv64-zbp.c16 long grev(long rs1, long rs2) in grev() argument
48 int grevw(int rs1, int rs2) in grevw() argument
80 long gorc(long rs1, long rs2) in gorc() argument
112 int gorcw(int rs1, int rs2) in gorcw() argument
144 long shfl(long rs1, long rs2) in shfl() argument
176 int shflw(int rs1, int rs2) in shflw() argument
208 long unshfl(long rs1, long rs2) in unshfl() argument
240 int unshflw(int rs1, int rs2) in unshflw() argument
272 long xperm_n(long rs1, long rs2) in xperm_n() argument
288 long xperm_b(long rs1, long rs2) in xperm_b() argument
[all …]
H A Driscv32-zbp.c16 long grev(long rs1, long rs2) in grev() argument
18 return __builtin_riscv_grev_32(rs1, rs2); in grev()
48 long gorc(long rs1, long rs2) in gorc() argument
50 return __builtin_riscv_gorc_32(rs1, rs2); in gorc()
80 long shfl(long rs1, long rs2) in shfl() argument
82 return __builtin_riscv_shfl_32(rs1, rs2); in shfl()
112 long unshfl(long rs1, long rs2) in unshfl() argument
144 long xperm_n(long rs1, long rs2) in xperm_n() argument
146 return __builtin_riscv_xperm_n(rs1, rs2); in xperm_n()
160 long xperm_b(long rs1, long rs2) in xperm_b() argument
[all …]
H A Driscv64-zbt.c23 int fsl(int rs1, int rs2, int rs3) { in fsl() argument
24 return __builtin_riscv_fsl_32(rs1, rs2, rs3); in fsl()
45 int fsr(int rs1, int rs2, int rs3) { in fsr() argument
46 return __builtin_riscv_fsr_32(rs1, rs2, rs3); in fsr()
63 int fsri(int rs1, int rs2) { in fsri() argument
64 return __builtin_riscv_fsr_32(rs1, rs2, 15); in fsri()
81 long fslw(long rs1, long rs2, long rs3) { in fslw() argument
82 return __builtin_riscv_fsl_64(rs1, rs2, rs3); in fslw()
99 long fsrw(long rs1, long rs2, long rs3) { in fsrw() argument
114 long fsriw(long rs1, long rs2) { in fsriw() argument
[all …]
H A Driscv64-zbe.c16 int bcompressw(int rs1, int rs2) { in bcompressw() argument
17 return __builtin_riscv_bcompress_32(rs1, rs2); in bcompressw()
31 int bdecompressw(int rs1, int rs2) { in bdecompressw() argument
32 return __builtin_riscv_bdecompress_32(rs1, rs2); in bdecompressw()
46 long bcompress(long rs1, long rs2) { in bcompress() argument
47 return __builtin_riscv_bcompress_64(rs1, rs2); in bcompress()
61 long bdecompress(long rs1, long rs2) { in bdecompress() argument
62 return __builtin_riscv_bdecompress_64(rs1, rs2); in bdecompress()
H A Driscv32-zbt.c19 int fsl(int rs1, int rs2, int rs3) { in fsl() argument
20 return __builtin_riscv_fsl_32(rs1, rs2, rs3); in fsl()
37 int fsr(int rs1, int rs2, int rs3) { in fsr() argument
38 return __builtin_riscv_fsr_32(rs1, rs2, rs3); in fsr()
52 int fsri(int rs1, int rs2) { in fsri() argument
53 return __builtin_riscv_fsr_32(rs1, rs2, 15); in fsri()
H A Driscv64-zbkx.c16 long xperm8(long rs1, long rs2) in xperm8() argument
18 return __builtin_riscv_xperm8(rs1, rs2); in xperm8()
32 long xperm4(long rs1, long rs2) in xperm4() argument
34 return __builtin_riscv_xperm4(rs1, rs2); in xperm4()
H A Driscv32-zbe.c16 long bcompress(long rs1, long rs2) { in bcompress() argument
17 return __builtin_riscv_bcompress_32(rs1, rs2); in bcompress()
31 long bdecompress(long rs1, long rs2) { in bdecompress() argument
32 return __builtin_riscv_bdecompress_32(rs1, rs2); in bdecompress()
H A Driscv32-zbkx.c16 long xperm8(long rs1, long rs2) in xperm8() argument
18 return __builtin_riscv_xperm8(rs1, rs2); in xperm8()
32 long xperm4(long rs1, long rs2) in xperm4() argument
34 return __builtin_riscv_xperm4(rs1, rs2); in xperm4()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcInstrVIS.td30 let rd = 0, rs1 = 0, rs2 = 0 in
35 let rs2 = 0 in
175 "cmask8 $rs2", []>;
177 "cmask16 $rs2", []>;
179 "cmask32 $rs2", []>;
242 (ins I64Regs:$rs2), "lzcnt $rs2, $rd", []>;
246 (ins DFPRegs:$rs2), "movstosw $rs2, $rd", []>;
248 (ins DFPRegs:$rs2), "movstouw $rs2, $rd", []>;
250 (ins DFPRegs:$rs2), "movdtox $rs2, $rd", []>;
252 (ins I64Regs:$rs2), "movdtox $rs2, $rd", []>;
[all …]
H A DSparcInstrAliases.td163 // t<cond> rs1 + rs2 => t<cond> %icc, rs1 + rs2
197 // t<cond> rs1 + rs2
354 def : InstAlias<"tst $rs2", (ORCCrr G0, IntRegs:$rs2, G0)>;
439 def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>;
452 def : InstAlias<"mov $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>;
454 def : InstAlias<"mov $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>;
456 def : InstAlias<"mov $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>;
466 def : InstAlias<"wr $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>;
468 def : InstAlias<"wr $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>;
470 def : InstAlias<"wr $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>;
[all …]
H A DSparcInstrInfo.td483 let rd = 0, rs1 = 0, rs2 = 0 in
1094 let rs2 = 0 in
1119 let rs2 = 0, rs1 = 5 in
1138 "wr $rs1, $rs2, %psr", []>;
1147 "wr $rs1, $rs2, %wim", []>;
1156 "wr $rs1, $rs2, %tbr", []>;
1183 let rs1 = 0, rs2 = 0 in
1192 "fitos $rs2, $rd",
1197 "fitod $rs2, $rd",
1696 "pwr $rs1, $rs2, %psr", []>;
[all …]
H A DSparcInstr64Bit.td167 "add $rs1, $rs2, $rd, $sym",
193 "mulx $rs1, $rs2, $rd",
204 "sdivx $rs1, $rs2, $rd",
213 "udivx $rs1, $rs2, $rd",
442 "fxtos $rs2, $rd",
446 "fxtod $rs2, $rd",
451 "fxtoq $rs2, $rd",
456 "fstox $rs2, $rd",
460 "fdtox $rs2, $rd",
465 "fqtox $rs2, $rd",
[all …]
/llvm-project-15.0.7/clang/test/CodeGen/RISCV/rvk-intrinsics/
H A Driscv32-zknh.c64 int sha512sig0h(int rs1, int rs2) { in sha512sig0h() argument
65 return __builtin_riscv_sha512sig0h_32(rs1, rs2); in sha512sig0h()
79 int sha512sig0l(int rs1, int rs2) { in sha512sig0l() argument
80 return __builtin_riscv_sha512sig0l_32(rs1, rs2); in sha512sig0l()
94 int sha512sig1h(int rs1, int rs2) { in sha512sig1h() argument
95 return __builtin_riscv_sha512sig1h_32(rs1, rs2); in sha512sig1h()
109 int sha512sig1l(int rs1, int rs2) { in sha512sig1l() argument
110 return __builtin_riscv_sha512sig1l_32(rs1, rs2); in sha512sig1l()
124 int sha512sum0r(int rs1, int rs2) { in sha512sum0r() argument
125 return __builtin_riscv_sha512sum0r_32(rs1, rs2); in sha512sum0r()
[all …]
H A Driscv64-zkne.c20 int aes64es(int rs1, int rs2) { in aes64es() argument
21 return __builtin_riscv_aes64es_64(rs1, rs2); in aes64es()
39 int aes64esm(int rs1, int rs2) { in aes64esm() argument
40 return __builtin_riscv_aes64esm_64(rs1, rs2); in aes64esm()
H A Driscv32-zkne.c16 int aes32esi(int rs1, int rs2) { in aes32esi() argument
17 return __builtin_riscv_aes32esi_32(rs1, rs2, 3); in aes32esi()
31 int aes32esmi(int rs1, int rs2) { in aes32esmi() argument
32 return __builtin_riscv_aes32esmi_32(rs1, rs2, 3); in aes32esmi()
H A Driscv32-zknd.c16 int aes32dsi(int rs1, int rs2) { in aes32dsi() argument
17 return __builtin_riscv_aes32dsi_32(rs1, rs2, 3); in aes32dsi()
31 int aes32dsmi(int rs1, int rs2) { in aes32dsmi() argument
32 return __builtin_riscv_aes32dsmi_32(rs1, rs2, 3); in aes32dsmi()
H A Driscv32-zksed.c16 long sm4ks(long rs1, long rs2) { in sm4ks() argument
17 return __builtin_riscv_sm4ks(rs1, rs2, 0); in sm4ks()
32 long sm4ed(long rs1, long rs2) { in sm4ed() argument
33 return __builtin_riscv_sm4ed(rs1, rs2, 0); in sm4ed()
H A Driscv64-zksed.c16 long sm4ks(long rs1, long rs2) { in sm4ks() argument
17 return __builtin_riscv_sm4ks(rs1, rs2, 0); in sm4ks()
31 long sm4ed(long rs1, long rs2) { in sm4ed() argument
32 return __builtin_riscv_sm4ed(rs1, rs2, 0); in sm4ed()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo16Instr.td520 def : Pat<(setne sGPR:$rs1, sGPR:$rs2),
522 def : Pat<(seteq sGPR:$rs1, sGPR:$rs2),
524 def : Pat<(setuge sGPR:$rs1, sGPR:$rs2),
526 def : Pat<(setule sGPR:$rs1, sGPR:$rs2),
528 def : Pat<(setult sGPR:$rs1, sGPR:$rs2),
530 def : Pat<(setugt sGPR:$rs1, sGPR:$rs2),
532 def : Pat<(setlt sGPR:$rs1, sGPR:$rs2),
534 def : Pat<(setgt sGPR:$rs1, sGPR:$rs2),
536 def : Pat<(setge sGPR:$rs1, sGPR:$rs2),
538 def : Pat<(setle sGPR:$rs1, sGPR:$rs2),
[all …]
H A DCSKYInstrInfo.td1057 def : Pat<(Type (LoadOp (add GPR:$rs1, GPR:$rs2))), (Inst GPR:$rs1, GPR:$rs2, 0)>;
1058 def : Pat<(Type (LoadOp (add GPR:$rs1, (shl GPR:$rs2, (i32 1))))), (Inst GPR:$rs1, GPR:$rs2, 1)>;
1059 def : Pat<(Type (LoadOp (add GPR:$rs1, (shl GPR:$rs2, (i32 2))))), (Inst GPR:$rs1, GPR:$rs2, 2)>;
1060 def : Pat<(Type (LoadOp (add GPR:$rs1, (shl GPR:$rs2, (i32 3))))), (Inst GPR:$rs1, GPR:$rs2, 3)>;
1074 def : Pat<(StoreOp Type:$rs2, GPR:$rs1), (Inst Type:$rs2, GPR:$rs1, 0)>;
1089 def : Pat<(StoreOp Type:$rz, (add GPR:$rs1, GPR:$rs2)), (Inst Type:$rz, GPR:$rs1, GPR:$rs2, 0)>;
1190 def : Pat<(setne GPR:$rs1, GPR:$rs2),
1194 def : Pat<(setuge GPR:$rs1, GPR:$rs2),
1202 def : Pat<(setlt GPR:$rs1, GPR:$rs2),
1204 def : Pat<(setgt GPR:$rs1, GPR:$rs2),
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td40 def : Pat<(store type:$rs2, GPR:$rs1),
59 def : Pat<(store type:$rs2, GPR:$rs1),
71 def : Pat<(store m.Mask:$rs2, GPR:$rs1),
85 (op_type op_reg_class:$rs2))),
88 op_reg_class:$rs2,
107 xop_kind:$rs2,
148 (xop_type xop_kind:$rs2),
792 def : Pat<(mti.Mask (and VR:$rs1, VR:$rs2)),
795 def : Pat<(mti.Mask (or VR:$rs1, VR:$rs2)),
798 def : Pat<(mti.Mask (xor VR:$rs1, VR:$rs2)),
[all …]
H A DRISCVInstrInfoVVLPatterns.td360 xop_kind:$rs2,
588 fti.RegClass:$rs2,
678 (vti_m1.Vector VR:$rs2),
845 (op vti.RegClass:$rs2,
856 (op vti.RegClass:$rs2,
1171 vti.RegClass:$rs2, vti.RegClass:$rs2, vti.RegClass:$rs1,
1179 vti.RegClass:$rs2, vti.RegClass:$rs2, GPR:$rs1,
1187 vti.RegClass:$rs2, vti.RegClass:$rs2, simm5:$rs1,
1375 fvti.RegClass:$rs2, fvti.RegClass:$rs2, fvti.RegClass:$rs1, (fvti.Mask V0),
1383 fvti.RegClass:$rs2, fvti.RegClass:$rs2,
[all …]
H A DRISCVInstrInfoC.td274 OpcodeStr, "$rd, $rs2"> {
523 let rs2 = 0;
536 isCall=1, Defs=[X1], rs2 = 0 in
701 def : InstAlias<"c.sw $rs2, (${rs1})", (C_SW GPRC:$rs2, GPRC:$rs1, 0)>;
703 def : InstAlias<"c.swsp $rs2, (${rs1})", (C_SWSP GPRC:$rs2, SP:$rs1, 0)>;
708 def : InstAlias<"c.sd $rs2, (${rs1})", (C_SD GPRC:$rs2, GPRC:$rs1, 0)>;
710 def : InstAlias<"c.sdsp $rs2, (${rs1})", (C_SDSP GPRC:$rs2, SP:$rs1, 0)>;
715 def : InstAlias<"c.fsw $rs2, (${rs1})", (C_FSW FPR32C:$rs2, GPRC:$rs1, 0)>;
717 def : InstAlias<"c.fswsp $rs2, (${rs1})", (C_FSWSP FPR32C:$rs2, SP:$rs1, 0)>;
722 def : InstAlias<"c.fsd $rs2, (${rs1})", (C_FSD FPR64C:$rs2, GPRC:$rs1, 0)>;
[all …]
H A DRISCVInstrInfoZb.td258 let rs2 = funct5;
819 def : Pat<(and GPR:$rs1, (not GPR:$rs2)), (ANDN GPR:$rs1, GPR:$rs2)>;
820 def : Pat<(or GPR:$rs1, (not GPR:$rs2)), (ORN GPR:$rs1, GPR:$rs2)>;
821 def : Pat<(xor GPR:$rs1, (not GPR:$rs2)), (XNOR GPR:$rs1, GPR:$rs2)>;
845 (BCLR GPR:$rs1, GPR:$rs2)>;
846 def : Pat<(and (rotl -2, GPR:$rs2), GPR:$rs1), (BCLR GPR:$rs1, GPR:$rs2)>;
848 (BSET GPR:$rs1, GPR:$rs2)>;
850 (BINV GPR:$rs1, GPR:$rs2)>;
852 (BEXT GPR:$rs1, GPR:$rs2)>;
855 (BSET X0, GPR:$rs2)>;
[all …]
H A DRISCVInstrInfoF.td196 (ins rty:$rs1, rty:$rs2), opcodestr, "$rd, $rs1, $rs2"> {
239 let rs2 = rs2val;
256 let rs2 = rs2val;
282 (ins rty:$rs1, rty:$rs2), opcodestr, "$rd, $rs1, $rs2"> {
404 def : InstAlias<"fsw $rs2, (${rs1})", (FSW FPR32:$rs2, GPR:$rs1, 0), 0>;
475 : Pat<(OpNode Ty:$rs1, Ty:$rs2, Cond), (Inst $rs1, $rs2)>;
479 : Pat<(OpNode RegTy:$rs1, RegTy:$rs2), (Inst $rs1, $rs2)>;
483 : Pat<(OpNode RegTy:$rs1, RegTy:$rs2), (Inst $rs1, $rs2, 0b111)>;
509 def : Pat<(fcopysign FPR32:$rs1, (fneg FPR32:$rs2)), (FSGNJN_S $rs1, $rs2)>;
511 // fmadd: rs1 * rs2 + rs3
[all …]

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