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/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.td232 let rs = 1;
237 let rs = 0;
289 "call\t$rs", [(MSP430call GR16:$rs)]>;
305 let rs = 1;
309 def PUSH8r : II8r<0b100, (outs), (ins GR8:$rs), "push.b\t$rs", []>;
310 def PUSH16r : II16r<0b100, (outs), (ins GR16:$rs), "push\t$rs", []>;
688 def RRA8n : II8n<0b010, (outs), (ins indreg:$rs), "rra.b\t$rs", []>;
689 def RRA16n : II16n<0b010, (outs), (ins indreg:$rs), "rra\t$rs", []>;
691 def RRA16p : II16p<0b010, (outs), (ins postreg:$rs), "rra\t$rs", []>;
705 def RRC8n : II8n<0b000, (outs), (ins indreg:$rs), "rrc.b\t$rs", []>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMicroMipsDSPInstrFormats.td26 bits<5> rs;
38 bits<5> rs;
49 bits<5> rs;
62 bits<5> rs;
75 bits<5> rs;
87 bits<5> rs;
100 bits<5> rs;
113 bits<5> rs;
126 bits<5> rs;
152 bits<5> rs;
[all …]
H A DMips64InstrInfo.td996 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs,
1004 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs,
1012 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs,
1210 def : MipsInstAlias<"nor\t$rs, $imm", (NORImm64 GPR64Opnd:$rs, GPR64Opnd:$rs,
1215 def : MipsInstAlias<"slt\t$rs, $imm", (SLTImm64 GPR64Opnd:$rs, GPR64Opnd:$rs,
1220 def : MipsInstAlias<"sltu\t$rs, $imm", (SLTUImm64 GPR64Opnd:$rs, GPR64Opnd:$rs,
1226 def : MipsInstAlias<"sge $rs, $imm", (SGEImm64 GPR64Opnd:$rs,
1233 def : MipsInstAlias<"sgeu $rs, $imm", (SGEUImm64 GPR64Opnd:$rs,
1240 def : MipsInstAlias<"sgt $rs, $imm", (SGTImm64 GPR64Opnd:$rs,
1247 def : MipsInstAlias<"sgtu $rs, $imm", (SGTUImm64 GPR64Opnd:$rs,
[all …]
H A DMicroMipsInstrFormats.td59 bits<3> rs;
72 bits<3> rs;
85 bits<3> rs;
111 bits<3> rs;
180 bits<5> rs;
202 bits<5> rs;
222 bits<5> rs;
254 bits<3> rs;
276 bits<3> rs;
297 bits<5> rs;
[all …]
H A DMicroMips32r6InstrFormats.td47 bits<3> rs;
58 bits<5> rs;
69 bits<5> rs;
82 bits<5> rs;
145 bits<5> rs;
159 bits<5> rs;
224 bits<5> rs;
263 bits<5> rs;
302 bits<5> rs;
315 bits<5> rs;
[all …]
H A DMipsDSPInstrFormats.td67 bits<5> rs;
81 bits<5> rs;
94 bits<5> rs;
107 bits<5> rs;
121 bits<5> rs;
194 bits<5> rs;
209 bits<5> rs;
224 bits<5> rs;
240 bits<5> rs;
269 bits<5> rs;
[all …]
H A DMipsInstrFormats.td156 bits<5> rs;
218 bits<5> rs;
263 bits<5> rs;
316 bits<5> rs;
340 bits<5> rs;
366 bits<5> rs;
394 bits<5> rs;
457 bits<5> rs;
488 bits<5> rs;
502 bits<5> rs;
[all …]
H A DMipsInstrInfo.td1563 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], II_JR,
2282 MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)],
2688 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
2711 def : MipsInstAlias<"sge $rs, $imm", (SGEImm GPR32Opnd:$rs,
2725 def : MipsInstAlias<"sgeu $rs, $imm", (SGEUImm GPR32Opnd:$rs,
2740 def : MipsInstAlias<"sgt $rs, $imm", (SGTImm GPR32Opnd:$rs,
2754 def : MipsInstAlias<"sgtu $rs, $imm", (SGTUImm GPR32Opnd:$rs,
2768 def : MipsInstAlias<"sle $rs, $imm", (SLEImm GPR32Opnd:$rs,
2880 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
2945 def : MipsInstAlias<"nor\t$rs, $imm", (NORImm GPR32Opnd:$rs, GPR32Opnd:$rs,
[all …]
H A DMips32r6InstrFormats.td177 bits<5> rs;
273 bits<5> rs;
285 bits<5> rs;
297 bits<5> rs;
340 bits<5> rs;
354 bits<5> rs;
378 // BEQC/BNEC require that rs < rt && rs != 0
380 bits<5> rs;
423 bits<5> rs; // rs != 0
455 bits<5> rs;
[all …]
H A DMicroMipsInstrInfo.td426 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
436 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
455 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
464 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
496 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
1357 "sgt $rd, $rs, $rt",
1360 "sgt $rs, $rt",
1361 (SLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1366 "sgtu $rs, $rt",
1367 (SLTu_MM GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Dpr13291-i1-store.ll7 ; PTX32: mov.u16 %rs{{[0-9]+}}, 0;
8 ; PTX32-NEXT: st.global.u8 [%r{{[0-9]+}}], %rs{{[0-9]+}};
9 ; PTX64: mov.u16 %rs{{[0-9]+}}, 0;
10 ; PTX64-NEXT: st.global.u8 [%rd{{[0-9]+}}], %rs{{[0-9]+}};
17 ; PTX32: ld.global.u8 %rs{{[0-9]+}}, [%r{{[0-9]+}}]
18 ; PTX32: and.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, 1;
19 ; PTX32: setp.eq.b16 %p{{[0-9]+}}, %rs{{[0-9]+}}, 1;
20 ; PTX64: ld.global.u8 %rs{{[0-9]+}}, [%rd{{[0-9]+}}]
21 ; PTX64: and.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, 1;
22 ; PTX64: setp.eq.b16 %p{{[0-9]+}}, %rs{{[0-9]+}}, 1;
H A Darithmetic-int.ll228 ; CHECK: add.s16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}
235 ; CHECK: sub.s16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}
242 ; CHECK: mul.lo.s16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}
249 ; CHECK: div.s16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}
256 ; CHECK: div.u16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}
263 ; CHECK: rem.s16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}
270 ; CHECK: rem.u16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}
277 ; CHECK: and.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}
284 ; CHECK: or.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}
291 ; CHECK: xor.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}
[all …]
H A Dvec8.ll8 ; CHECK-DAG: ld.param.v4.u8 {[[E0:%rs[0-9]+]], [[E1:%rs[0-9]+]], [[E2:%rs[0-9]+]], [[E3:%rs[0-9]+]]…
9 ; CHECK-DAG: ld.param.v4.u8 {[[E4:%rs[0-9]+]], [[E5:%rs[0-9]+]], [[E6:%rs[0-9]+]], [[E7:%rs[0-9]+]]…
11 ; CHECK: add.s16 [[T:%rs[0-9+]]], [[E1]], [[E6]];
H A Dstore-retval.ll49 …; CHECK-NOT: st.param.v4.b8 [func_retval0+20], {%rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}, %r…
67 …; CHECK-NOT: st.param.v4.b8 [func_retval0+20], {%rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}, %r…
68 …; CHECK-NOT: st.param.v4.b8 [func_retval0+24], {%rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}, %r…
69 …; CHECK-NOT: st.param.v4.b8 [func_retval0+28], {%rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}, %r…
H A Dcompare-int.ll199 ; CHECK: setp.eq.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
208 ; CHECK: setp.ne.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
217 ; CHECK: setp.gt.u16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
226 ; CHECK: setp.ge.u16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
235 ; CHECK: setp.lt.u16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
244 ; CHECK: setp.le.u16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
253 ; CHECK: setp.gt.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
262 ; CHECK: setp.ge.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
271 ; CHECK: setp.lt.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
280 ; CHECK: setp.le.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
[all …]
H A Dload-store.ll6 ; CHECK: ld.u8 %rs{{[0-9]+}}, [%rd{{[0-9]+}}]
9 ; CHECK: st.u8 [%rd{{[0-9]+}}], %rs{{[0-9]+}}
12 ; CHECK: ld.u16 %rs{{[0-9]+}}, [%rd{{[0-9]+}}]
15 ; CHECK: st.u16 [%rd{{[0-9]+}}], %rs{{[0-9]+}}
35 ; CHECK: ld.volatile.u8 %rs{{[0-9]+}}, [%rd{{[0-9]+}}]
38 ; CHECK: st.volatile.u8 [%rd{{[0-9]+}}], %rs{{[0-9]+}}
41 ; CHECK: ld.volatile.u16 %rs{{[0-9]+}}, [%rd{{[0-9]+}}]
44 ; CHECK: st.volatile.u16 [%rd{{[0-9]+}}], %rs{{[0-9]+}}
64 ; CHECK: ld.volatile.u8 %rs{{[0-9]+}}, [%rd{{[0-9]+}}]
67 ; CHECK: st.volatile.u8 [%rd{{[0-9]+}}], %rs{{[0-9]+}}
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A DPBQP-csr.ll14 %x.i = getelementptr inbounds %rs, %rs* %r, i64 0, i32 7, i32 0
15 %y.i = getelementptr inbounds %rs, %rs* %r, i64 0, i32 7, i32 1
16 %z.i = getelementptr inbounds %rs, %rs* %r, i64 0, i32 7, i32 2
17 %x.i61 = getelementptr inbounds %rs, %rs* %r, i64 0, i32 8, i32 0
18 %y.i62 = getelementptr inbounds %rs, %rs* %r, i64 0, i32 8, i32 1
19 %z.i63 = getelementptr inbounds %rs, %rs* %r, i64 0, i32 8, i32 2
20 %x.i58 = getelementptr inbounds %rs, %rs* %r, i64 0, i32 9, i32 0
21 %y.i59 = getelementptr inbounds %rs, %rs* %r, i64 0, i32 9, i32 1
23 %na = getelementptr inbounds %rs, %rs* %r, i64 0, i32 0
31 %fn = getelementptr inbounds %rs, %rs* %r, i64 0, i32 4
[all …]
/llvm-project-15.0.7/clang/test/Analysis/
H A Dmpichecker.cpp99 ReqStruct rs; in doubleNonblocking3() local
141 ReqStruct rs; in missingNonBlocking2() local
219 ReqStruct rs; in noDoubleRequestUsage() local
225 &rs.req); in noDoubleRequestUsage()
227 &rs.req2); in noDoubleRequestUsage()
238 ReqStruct rs; in noDoubleRequestUsage2() local
244 &rs.req[0]); in noDoubleRequestUsage2()
246 &rs.req[1]); in noDoubleRequestUsage2()
248 &rs.req2); in noDoubleRequestUsage2()
260 ReqStruct rs; in nestedRequest() local
[all …]
H A DMemRegion.cpp25 ReqStruct rs; in testGetDescriptiveName3() local
26 MPI_Request *r = &rs.req; in testGetDescriptiveName3()
34 ReqStruct rs; in testGetDescriptiveName4() local
35 MPI_Request *r = &rs.req[0][1]; in testGetDescriptiveName4()
44 ReqStruct rs; in testGetDescriptiveName5() local
45 MPI_Request *r = &rs.req.req; in testGetDescriptiveName5()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZb.td659 def : InstAlias<"zext.w $rd, $rs", (ADD_UW GPR:$rd, GPR:$rs, X0)>;
672 def : InstAlias<"rev.b $rd, $rs", (BREV8 GPR:$rd, GPR:$rs)>;
700 def : InstAlias<"rev16 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b10000)>;
702 def : InstAlias<"rev4 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11100)>;
703 def : InstAlias<"rev2 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11110)>;
704 def : InstAlias<"rev $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11111)>;
714 def : InstAlias<"orc16 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b10000)>;
715 def : InstAlias<"orc8 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11000)>;
1090 def : Pat<(i32 (and GPR:$rs, 0xFFFF)), (ZEXT_H_RV32 GPR:$rs)>;
1092 def : Pat<(i64 (and GPR:$rs, 0xFFFF)), (ZEXT_H_RV64 GPR:$rs)>;
[all …]
H A DRISCVInstrInfoD.td209 def : InstAlias<"fmv.d $rd, $rs", (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
210 def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
211 def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
215 def : InstAlias<"fgt.d $rd, $rs, $rt",
217 def : InstAlias<"fge.d $rd, $rs, $rt",
229 def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D_INX FPR64INX:$rd, FPR64INX:$rs, FPR64INX:$rs)>;
230 def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D_INX FPR64INX:$rd, FPR64INX:$rs, FPR64INX:$rs)>;
232 def : InstAlias<"fgt.d $rd, $rs, $rt",
234 def : InstAlias<"fge.d $rd, $rs, $rt",
239 def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D_IN32X FPR64IN32X:$rd, FPR64IN32X:$rs, FPR64IN32X:$rs)>;
[all …]
/llvm-project-15.0.7/clang/test/CodeGen/PowerPC/
H A Dbuiltins-ppc-xlcompat-rotate.c79 unsigned int testrotatel4(unsigned int rs, unsigned int shift) { in testrotatel4() argument
80 return __rotatel4(rs, shift); in testrotatel4()
87 unsigned long long testrotatel8(unsigned long long rs, unsigned long long shift) { in testrotatel8() argument
88 return __rotatel8(rs, shift); in testrotatel8()
96 unsigned long long testrdlam(unsigned long long rs, unsigned int shift) { in testrdlam() argument
99 return __rdlam(rs, shift, 7); in testrdlam()
/llvm-project-15.0.7/lldb/third_party/Python/module/pexpect-4.6/pexpect/
H A Dscreen.py153 def fill_region (self, rs,cs, re,ce, ch=SPACE): argument
158 rs = constrain (rs, 1, self.rows)
162 if rs > re:
163 rs, re = re, rs
166 for r in range (rs, re+1):
252 def get_region (self, rs,cs, re,ce): argument
256 rs = constrain (rs, 1, self.rows)
260 if rs > re:
261 rs, re = re, rs
265 for r in range (rs, re+1):
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32r6/
H A Dvalid.s4 # rs == 0
5 # rs != 0
8 # rs < rt
9 # rs == rt
10 # rs > rt
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r6/
H A Dvalid.s4 # rs == 0
5 # rs != 0
8 # rs < rt
9 # rs == rt
10 # rs > rt

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