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/llvm-project-15.0.7/llvm/test/MC/M68k/ShiftRotate/Classes/
H A DMxSR_DI.s27 ; CHECK: ror.b #1, %d1
29 ror.b #1, %d1
30 ; CHECK: ror.l #1, %d1
32 ror.l #1, %d1
35 ror.l #2, %d1
38 ror.l #3, %d1
41 ror.l #4, %d1
44 ror.l #5, %d1
47 ror.l #6, %d1
50 ror.l #7, %d1
[all …]
H A DMxSR_DD.s27 ; CHECK: ror.b %d0, %d1
29 ror.b %d0, %d1
30 ; CHECK: ror.l %d0, %d1
32 ror.l %d0, %d1
/llvm-project-15.0.7/llvm/test/MC/AVR/
H A Dinst-ror.s7 ror r31
8 ror r25
9 ror r5
10 ror r0
12 ; CHECK: ror r31 ; encoding: [0xf7,0x95]
13 ; CHECK: ror r25 ; encoding: [0x97,0x95]
14 ; CHECK: ror r5 ; encoding: [0x57,0x94]
17 ; CHECK-INST: ror r31
18 ; CHECK-INST: ror r25
19 ; CHECK-INST: ror r5
[all …]
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Darm64-logical-encoding.s58 and w1, w2, w3, ror #2
59 and x1, x2, x3, ror #2
102 bic w1, w2, w3, ror #3
103 bic x1, x2, x3, ror #3
146 eon w1, w2, w3, ror #4
147 eon x1, x2, x3, ror #4
168 eor w1, w2, w3, ror #5
169 eor x1, x2, x3, ror #5
190 orr w1, w2, w3, ror #6
191 orr x1, x2, x3, ror #6
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/ARM/
H A Dcortex-a57-basic-instructions.s32 adc r4, r5, r6, ror #1
33 adc pc, r5, r6, ror #2
34 adc r4, r5, r6, ror #31
39 adc r6, r7, r8, ror r9
50 adc r4, r4, r5, ror #1
56 adc r6, r6, r7, ror r9
171 cmn r1, r6, ror #10
175 cmn r7, r8, ror r2
185 cmp r1, r6, ror #10
189 cmp r7, r8, ror r2
[all …]
H A Dcortex-a57-thumb.s18 adc.w r0, r1, r3, ror #4
36 add.w r4, r8, r1, ror #12
125 cmp.w r1, r4, ror #15
423 mvn.w r5, r6, ror #6
516 ror.w r2, r3, #12
519 ror.w r2, r3, #4
521 ror.w r3, r3, #19
524 ror.w r12, r12, #21
525 ror.w r3, r4, r2
526 ror.w r1, r1, r2
[all …]
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dbasic-arm-instructions.s98 adc r4, r5, ror #1
99 adc r4, r5, ror #31
104 adc r6, r7, ror r9
224 add r4, r5, ror #5
228 add r6, r7, ror r9
372 and r10, r1, ror #10
376 and r6, r7, ror r2
1955 ror r2, r4, #31
1956 ror r2, r4, #1
1957 ror r2, r4, #0
[all …]
H A Darm-shift-encoding.s11 ldr r0, [r0, r0, ror #16]
21 @ CHECK: ldr r0, [r0, r0, ror #16] @ encoding: [0x60,0x08,0x90,0xe7]
31 pld [r0, r0, ror #16]
41 @ CHECK: [r0, r0, ror #16] @ encoding: [0x60,0xf8,0xd0,0xf7]
51 str r0, [r0, r0, ror #16]
61 @ CHECK: str r0, [r0, r0, ror #16] @ encoding: [0x60,0x08,0x80,0xe7]
69 ldr r3, [r4], r5, ror #0
89 adc r8, r1, r0, ror #16
99 @ CHECK: adc r8, r1, r0, ror #16 @ encoding: [0x60,0x88,0xa1,0xe0]
109 cmp r8, r1, ror #16
[all …]
H A Dbasic-thumb2-instructions.s48 adc r0, r1, r3, ror #4
480 bic r12, r6, ror #29
584 cmn r1, r6, ror #10
604 cmp r1, r4, ror #15
1843 mvn r5, r6, ror #6
2205 ror r2, r3, #12
2208 ror r2, r3, #4
2211 ror r3, #19
2214 ror.w r12, #21
2231 ror r3, r4, r2
[all …]
H A Dthumb2-dsp-diag.s8 sxtb16 r0, r0, ror #8
18 @ CHECK-7EM: sxtb16 r0, r0, ror #8 @ encoding: [0x2f,0xfa,0x90,0xf0]
24 uxtb16 r0, r0, ror #8
34 @ CHECK-7EM: uxtb16 r0, r0, ror #8 @ encoding: [0x3f,0xfa,0x90,0xf0]
H A Dthumb-shift-encoding.s15 sbc.w r8, r1, r0, ror #16
25 @ CHECK: sbc.w r8, r1, r0, ror #16 @ encoding: [0x61,0xeb,0x30,0x48]
35 and.w r8, r1, r0, ror #16
45 @ CHECK: and.w r8, r1, r0, ror #16 @ encoding: [0x01,0xea,0x30,0x48]
/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Drotations32.s50 ror $4,$5
56 ror $4,$5,$6
62 ror $4,0
65 ror $4,$5,0
68 ror $4,1
73 ror $4,$5,1
78 ror $4,2
83 ror $4,$5,2
H A Drotations64.s50 ror $4,$5
56 ror $4,$5,$6
62 ror $4,0
65 ror $4,$5,0
68 ror $4,1
73 ror $4,$5,1
78 ror $4,2
83 ror $4,$5,2
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dror.ll4 ; rotr (rotr x, 4), 6 -> rotr x, 10 -> ror r0, r0, #10
8 ; CHECK-NEXT: ror r0, r0, #10
16 ; rotl (rotr x, 4), 6 -> rotl x, 2 -> ror r0, r0, #30
20 ; CHECK-NEXT: ror r0, r0, #30
32 ; CHECK-NEXT: ror r0, r0, #10
33 ; CHECK-NEXT: ror r1, r1, #10
44 ; CHECK-NEXT: ror r0, r0, #30
45 ; CHECK-NEXT: ror r1, r1, #30
H A Dacle-intrinsics-rot.ll8 ; CHECK: sxtb16 r0, r0, ror #8
19 ; CHECK: sxtb16 r0, r0, ror #16
30 ; CHECK: sxtb16 r0, r0, ror #24
41 ; CHECK: uxtb16 r0, r0, ror #8
52 ; CHECK: uxtb16 r0, r0, ror #16
63 ; CHECK: uxtb16 r0, r0, ror #24
74 ; CHECK: sxtab16 r0, r0, r1, ror #8
85 ; CHECK: sxtab16 r0, r0, r1, ror #16
96 ; CHECK: sxtab16 r0, r0, r1, ror #24
107 ; CHECK: uxtab16 r0, r0, r1, ror #8
[all …]
H A Dfunnel-shift-rot.ll63 ; CHECK-NEXT: ror r0, r0, r1
99 ; SCALAR-NEXT: ror r0, r0, r12
102 ; SCALAR-NEXT: ror r1, r1, r12
105 ; SCALAR-NEXT: ror r2, r2, r12
108 ; SCALAR-NEXT: ror r3, r3, r12
137 ; SCALAR-NEXT: ror r0, r0, #29
138 ; SCALAR-NEXT: ror r1, r1, #29
139 ; SCALAR-NEXT: ror r2, r2, #29
140 ; SCALAR-NEXT: ror r3, r3, #29
175 ; CHECK-NEXT: ror r0, r0, #3
[all …]
H A Duxtb.ll16 ; CHECK-NEXT: uxtb16 r0, r0, ror #8
26 ; CHECK-NEXT: uxtb16 r0, r0, ror #8
36 ; CHECK-NEXT: uxtb16 r0, r0, ror #8
46 ; CHECK-NEXT: uxtb16 r0, r0, ror #8
56 ; CHECK-NEXT: uxtb16 r0, r0, ror #16
69 ; CHECK-NEXT: uxtb16 r0, r0, ror #16
82 ; CHECK-NEXT: uxtb16 r0, r0, ror #24
94 ; CHECK-NEXT: uxtb16 r0, r0, ror #24
H A Dcmp.ll67 ; CHECK: subs r0, r0, r0, ror #8
69 ; CHECK-T2: subs.w r0, r0, r0, ror #8
126 ; CHECK: cmp r1, r0, ror #11
129 ; CHECK-T2: cmp.w r1, r0, ror #11
135 %ror = or i32 %lsr, %lsl
136 %cmp = icmp uge i32 %ror, %b
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AArch64/
H A Darm64-logical.txt68 # CHECK: and w1, w2, w3, ror #2
69 # CHECK: and x1, x2, x3, ror #2
90 # CHECK: ands w1, w2, w3, ror #2
91 # CHECK: ands x1, x2, x3, ror #2
112 # CHECK: bic w1, w2, w3, ror #3
113 # CHECK: bic x1, x2, x3, ror #3
156 # CHECK: eon w1, w2, w3, ror #4
157 # CHECK: eon x1, x2, x3, ror #4
178 # CHECK: eor w1, w2, w3, ror #5
179 # CHECK: eor x1, x2, x3, ror #5
[all …]
/llvm-project-15.0.7/compiler-rt/lib/builtins/arm/
H A Dbswapdi2.S25 eor r2, r0, r0, ror #16
28 eor r2, r2, r0, ror #8
30 eor r0, r1, r1, ror #16
33 eor r0, r0, r1, ror #8
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dbasic-arm-instructions.txt53 # CHECK: adc r4, r5, r6, ror #1
54 # CHECK: adc r4, r5, r6, ror #31
59 # CHECK: adc r6, r7, r8, ror r9
71 # CHECK: adc r4, r4, r5, ror #1
72 # CHECK: adc r4, r4, r5, ror #31
77 # CHECK: adc r6, r6, r7, ror r9
430 # CHECK: cmn r1, r6, ror #10
434 # CHECK: cmn r7, r8, ror r2
463 # CHECK: cmp r1, r6, ror #10
467 # CHECK: cmp r7, r8, ror r2
[all …]
H A Dthumb2.txt33 # CHECK: adc.w r0, r1, r3, ror #4
81 # CHECK: add.w r4, r8, r1, ror #12
309 #CHECK: cmn.w r1, r6, ror #10
329 #CHECK: cmp.w r1, r4, ror #15
1193 # CHECK: mvn.w r5, r6, ror #6
1494 # CHECK: ror.w r2, r3, #12
1497 # CHECK: ror.w r2, r3, #4
1500 # CHECK: ror.w r3, r3, #19
1503 # CHECK: ror.w r12, r12, #21
1520 # CHECK: ror.w r3, r4, r2
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/M68k/ShiftRotate/
H A Dror.ll15 ; CHECK-NEXT: ror.b %d0, %d1
28 ; CHECK-NEXT: ror.w %d0, %d1
41 ; CHECK-NEXT: ror.l %d1, %d0
53 ; CHECK-NEXT: ror.b #3, %d0
64 ; CHECK-NEXT: ror.w #5, %d0
75 ; CHECK-NEXT: ror.l #7, %d0
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dthumb2-uxtb.ll26 ; CHECK-DSP-NEXT: uxtb16 r0, r0, ror #8
42 ; CHECK-DSP-NEXT: uxtb16 r0, r0, ror #8
58 ; CHECK-DSP-NEXT: uxtb16 r0, r0, ror #8
74 ; CHECK-DSP-NEXT: uxtb16 r0, r0, ror #8
90 ; CHECK-DSP-NEXT: uxtb16 r0, r0, ror #16
96 ; CHECK-NO-DSP-NEXT: and.w r0, r1, r0, ror #16
109 ; CHECK-DSP-NEXT: uxtb16 r0, r0, ror #16
115 ; CHECK-NO-DSP-NEXT: and.w r0, r1, r0, ror #16
128 ; CHECK-DSP-NEXT: uxtb16 r0, r0, ror #24
134 ; CHECK-NO-DSP-NEXT: and.w r0, r1, r0, ror #24
[all …]
H A Dthumb2-uxt_rot.ll51 ; CHECK-DSP-NEXT: uxtab r0, r0, r1, ror #16
69 ; CHECK-DSP-NEXT: uxtah r0, r0, r1, ror #8
87 ; CHECK-DSP-NEXT: uxtab r0, r0, r1, ror #8
105 ; CHECK-DSP-NEXT: uxtah r0, r0, r1, ror #24
110 ; CHECK-NO-DSP-NEXT: ror.w r1, r1, #24
126 ; CHECK-DSP-NEXT: uxtah r0, r0, r1, ror #24
131 ; CHECK-NO-DSP-NEXT: ror.w r1, r1, #24

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