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Searched refs:rol (Results 1 – 25 of 39) sorted by relevance

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/llvm-project-15.0.7/llvm/test/MC/AVR/
H A Dinst-rol.s7 rol r31
8 rol r25
9 rol r5
10 rol r0
12 ; CHECK: rol r31 ; encoding: [0xff,0x1f]
13 ; CHECK: rol r25 ; encoding: [0x99,0x1f]
14 ; CHECK: rol r5 ; encoding: [0x55,0x1c]
17 ; CHECK-INST: rol r31
18 ; CHECK-INST: rol r25
19 ; CHECK-INST: rol r5
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dv60rol-instrs.ll3 ; CHECK: r{{[0-9]*}} += rol(r{{[0-9]*}},#31)
4 ; CHECK: r{{[0-9]*}} &= rol(r{{[0-9]*}},#31)
5 ; CHECK: r{{[0-9]*}} -= rol(r{{[0-9]*}},#31)
6 ; CHECK: r{{[0-9]*}} |= rol(r{{[0-9]*}},#31)
7 ; CHECK: r{{[0-9]*}} ^= rol(r{{[0-9]*}},#31)
24 %v2 = call i32 @llvm.hexagon.S6.rol.i.r.acc(i32 0, i32 1, i32 31)
38 declare i32 @llvm.hexagon.S6.rol.i.r.acc(i32, i32, i32) #1
41 declare i32 @llvm.hexagon.S6.rol.i.r.and(i32, i32, i32) #1
44 declare i32 @llvm.hexagon.S6.rol.i.r.nac(i32, i32, i32) #1
47 declare i32 @llvm.hexagon.S6.rol.i.r.or(i32, i32, i32) #1
[all …]
H A Drotate.ll6 ; CHECK: r0 = rol(r0,#7)
30 ; CHECK: r0 = rol(r0,#25)
53 ; CHECK: r1:0 = rol(r1:0,#7)
79 ; CHECK: r1:0 = rol(r1:0,#57)
105 ; CHECK: r0 += rol(r1,#7)
116 ; CHECK: r0 -= rol(r1,#7)
127 ; CHECK: r0 &= rol(r1,#7)
150 ; CHECK: r0 ^= rol(r1,#7)
161 ; CHECK: r1:0 += rol(r3:2,#7)
172 ; CHECK: r1:0 -= rol(r3:2,#7)
[all …]
H A Dintrinsics-v60-misc.ll417 ; CHECK: r{{[0-9]+}} = rol(r{{[0-9]+}},#14)
427 ; CHECK: r{{[0-9]+}} += rol(r{{[0-9]+}},#12)
436 ; CHECK: r{{[0-9]+}} &= rol(r{{[0-9]+}},#18)
445 ; CHECK: r{{[0-9]+}} -= rol(r{{[0-9]+}},#31)
454 ; CHECK: r{{[0-9]+}} |= rol(r{{[0-9]+}},#30)
463 ; CHECK: r{{[0-9]+}} ^= rol(r{{[0-9]+}},#31)
581 declare i64 @llvm.hexagon.S6.rol.i.p(i64, i32) #0
582 declare i64 @llvm.hexagon.S6.rol.i.p.acc(i64, i64, i32) #0
585 declare i64 @llvm.hexagon.S6.rol.i.p.or(i64, i64, i32) #0
587 declare i32 @llvm.hexagon.S6.rol.i.r(i32, i32) #0
[all …]
H A Dv60_Q6_P_rol_PI.ll2 ; CHECK: r{{[0-9]*}}:{{[0-9]*}} = rol(r{{[0-9]*}}:{{[0-9]*}},#4)
18 %v2 = call i64 @llvm.hexagon.S6.rol.i.p(i64 483648, i32 4)
24 declare i64 @llvm.hexagon.S6.rol.i.p(i64, i32) #1
H A Drotate-multi.ll5 ; CHECK: r[[R00:[0-9]+]] = rol(r0,#7)
6 ; CHECK: r[[R00]] |= rol(r0,#9)
22 ; CHECK: r1 |= rol(r0,#9)
H A Drotl-i64.ll2 ; CHECK: rol
H A Dfunnel-shift.ll78 ; CHECK: r[[R80:[0-9]+]] = rol(r0,#17)
95 ; CHECK: r[[RA0:[0-9]+]]:[[RA1:[0-9]+]] = rol(r1:0,#17)
113 ; CHECK: r[[RC0:[0-9]+]] = rol(r0,#15)
130 ; CHECK: r[[RE0:[0-9]+]]:[[RE1:[0-9]+]] = rol(r1:0,#47)
/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Drotations32.s9 rol $4,$5
16 rol $4,$5,$6
23 rol $4,0
26 rol $4,$5,0
29 rol $4,1
34 rol $4,$5,1
39 rol $4,2
44 rol $4,$5,2
H A Drotations64.s9 rol $4,$5
16 rol $4,$5,$6
23 rol $4,0
26 rol $4,$5,0
29 rol $4,1
34 rol $4,$5,1
39 rol $4,2
44 rol $4,$5,2
/llvm-project-15.0.7/llvm/test/MC/M68k/ShiftRotate/Classes/
H A DMxSR_DD.s21 ; CHECK: rol.b %d6, %d7
23 rol.b %d6, %d7
24 ; CHECK: rol.l %d7, %d1
26 rol.l %d7, %d1
H A DMxSR_DI.s21 ; CHECK: rol.b #1, %d1
23 rol.b #1, %d1
24 ; CHECK: rol.l #1, %d1
26 rol.l #1, %d1
/llvm-project-15.0.7/llvm/test/CodeGen/M68k/ShiftRotate/
H A Drol.ll15 ; CHECK-NEXT: rol.b %d0, %d1
28 ; CHECK-NEXT: rol.w %d0, %d1
41 ; CHECK-NEXT: rol.l %d1, %d0
53 ; CHECK-NEXT: rol.b #3, %d0
64 ; CHECK-NEXT: rol.w #5, %d0
75 ; CHECK-NEXT: rol.l #7, %d0
/llvm-project-15.0.7/llvm/lib/Support/
H A DSHA1.cpp30 static inline uint32_t rol(uint32_t Number, int Bits) { in rol() function
45 E += ((B & (C ^ D)) ^ D) + blk0(Buf, I) + 0x5A827999 + rol(A, 5); in r0()
46 B = rol(B, 30); in r0()
51 E += ((B & (C ^ D)) ^ D) + blk(Buf, I) + 0x5A827999 + rol(A, 5); in r1()
52 B = rol(B, 30); in r1()
57 E += (B ^ C ^ D) + blk(Buf, I) + 0x6ED9EBA1 + rol(A, 5); in r2()
58 B = rol(B, 30); in r2()
63 E += (((B | C) & D) | (B & C)) + blk(Buf, I) + 0x8F1BBCDC + rol(A, 5); in r3()
64 B = rol(B, 30); in r3()
69 E += (B ^ C ^ D) + blk(Buf, I) + 0xCA62C1D6 + rol(A, 5); in r4()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AVR/
H A Dshift.ll38 ; CHECK-NEXT: rol r25
167 ; CHECK: rol r24
169 ; CHECK-NEXT: rol r24
201 ; CHECK-NEXT: rol r25
218 ; CHECK-NEXT: rol r25
220 ; CHECK-NEXT: rol r25
308 ; CHECK-NEXT: rol r24
346 ; CHECK-NEXT: rol r24
H A Delpm.ll12 ; CHECK-NEXT: rol r23
19 ; CHECK-NEXT: rol r25
41 ; CHECK-NEXT: rol r23
50 ; CHECK-NEXT: rol r25
72 ; CHECK-NEXT: rol r25
81 ; CHECK-NEXT: rol r23
103 ; CHECK-NEXT: rol r23
112 ; CHECK-NEXT: rol r25
H A Dlpmx.ll28 ; CHECK-O0-NEXT: rol r31
58 ; CHECK-O3-NEXT: rol r25
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dabsolute-rotate.ll31 %rol = or i64 %shr, %shl
32 %cmp = icmp ult i64 %rol, 109
/llvm-project-15.0.7/llvm/test/MC/M68k/
H A Dinstructions.s41 ; CHECK: rol.l #8, %d1
42 rol.l #8, %d1
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Drv32zbkb-valid.s15 # CHECK-ASM-AND-OBJ: rol t0, t1, t2
17 rol t0, t1, t2 label
H A Drv32zbbp-valid.s34 # CHECK-ASM-AND-OBJ: rol t0, t1, t2
36 rol t0, t1, t2 label
H A Drv32zbbp-invalid.s10 rol t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction label
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrShiftRotate.td460 "rol{b}\t{%cl, $dst|$dst, cl}",
463 "rol{w}\t{%cl, $dst|$dst, cl}",
466 "rol{l}\t{%cl, $dst|$dst, cl}",
491 "rol{b}\t$dst",
494 "rol{w}\t$dst",
497 "rol{l}\t$dst",
500 "rol{q}\t$dst",
539 "rol{b}\t$dst",
542 "rol{w}\t$dst",
546 "rol{l}\t$dst",
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/M68k/
H A Dshift-rotate.txt9 # CHECK: rol.l #5, %d1
/llvm-project-15.0.7/compiler-rt/lib/builtins/avr/
H A Dmulhi3.S62 rol r23 ; B <<= 1;

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