Home
last modified time | relevance | path

Searched refs:rn (Results 1 – 25 of 102) sorted by relevance

12345

/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Dmath-intrins-sm53-ptx42.ll4 declare half @llvm.nvvm.fma.rn.f16(half, half, half)
5 declare half @llvm.nvvm.fma.rn.ftz.f16(half, half, half)
6 declare half @llvm.nvvm.fma.rn.sat.f16(half, half, half)
16 ; CHECK: fma.rn.f16
24 ; CHECK: fma.rn.ftz.f16
32 ; CHECK: fma.rn.sat.f16
40 ; CHECK: fma.rn.ftz.sat.f16
48 ; CHECK: fma.rn.f16x2
56 ; CHECK: fma.rn.ftz.f16x2
64 ; CHECK: fma.rn.sat.f16x2
[all …]
H A Dconvert-sm80.ll8 ; CHECK: cvt.rn.bf16x2.f32
17 ; CHECK: cvt.rn.relu.bf16x2.f32
41 declare i32 @llvm.nvvm.ff2bf16x2.rn(float, float)
42 declare i32 @llvm.nvvm.ff2bf16x2.rn.relu(float, float)
49 ; CHECK: cvt.rn.f16x2.f32
58 ; CHECK: cvt.rn.relu.f16x2.f32
90 ; CHECK: cvt.rn.bf16.f32
91 %val = call i16 @llvm.nvvm.f2bf16.rn(float %f1);
99 ; CHECK: cvt.rn.relu.bf16.f32
123 declare i16 @llvm.nvvm.f2bf16.rn(float)
[all …]
H A Dfast-math.ll8 ; CHECK: sqrt.rn.f32
9 ; CHECK: div.rn.f32
17 ; CHECK: sqrt.rn.f32
65 ; CHECK: sqrt.rn.f64
66 ; CHECK: div.rn.f64
76 ; CHECK: div.rn.f64
85 ; CHECK: sqrt.rn.f32
118 ; CHECK: add.rn.f32
150 ; CHECK: rcp.rn.f32
151 ; CHECK: mul.rn.f32
[all …]
H A Dfp-contract.ll9 ;; If fusion is allowed, we try to form fma.rn at the PTX level, and emit
12 ;; we do not form fma.rn at the PTX level and explicitly generate add.rn
18 ;; FAST: fma.rn.f32
19 ;; DEFAULT: mul.rn.f32
20 ;; DEFAULT: add.rn.f32
29 ;; We cannot form an fma here, but make sure we explicitly emit add.rn.f32
32 ;; DEFAULT: add.rn.f32
H A Dconvert-fp.ll44 ; CHECK: cvt.rn.f32.u16 %f{{[0-9]+}}, %rs{{[0-9]+}};
50 ; CHECK: cvt.rn.f32.u32 %f{{[0-9]+}}, %r{{[0-9]+}};
56 ; CHECK: cvt.rn.f32.u64 %f{{[0-9]+}}, %rd{{[0-9]+}};
62 ; CHECK: cvt.rn.f64.u16 %fd{{[0-9]+}}, %rs{{[0-9]+}};
68 ; CHECK: cvt.rn.f64.u32 %fd{{[0-9]+}}, %r{{[0-9]+}};
81 ; CHECK: cvt.rn.f32.f64 %f{{[0-9]+}}, %fd{{[0-9]+}};
94 ; CHECK: cvt.rn.f32.s16 %f{{[0-9]+}}, %rs{{[0-9]+}}
100 ; CHECK: cvt.rn.f32.s32 %f{{[0-9]+}}, %r{{[0-9]+}}
106 ; CHECK: cvt.rn.f32.s64 %f{{[0-9]+}}, %rd{{[0-9]+}}
112 ; CHECK: cvt.rn.f64.s16 %fd{{[0-9]+}}, %rs{{[0-9]+}}
[all …]
H A Dfma-disable.ll12 ; FMA: fma.rn.f32
13 ; MUL: mul.rn.f32
14 ; MUL: add.rn.f32
22 ; FMA: fma.rn.f64
23 ; MUL: mul.rn.f64
24 ; MUL: add.rn.f64
H A Dmath-intrins-sm80-ptx70.ll43 declare i16 @llvm.nvvm.fma.rn.bf16(i16, i16, i16)
44 declare i16 @llvm.nvvm.fma.rn.relu.bf16(i16, i16, i16)
45 declare i32 @llvm.nvvm.fma.rn.bf16x2(i32, i32, i32)
307 ; CHECK: fma.rn.relu.f16
315 ; CHECK: fma.rn.ftz.relu.f16
323 ; CHECK: fma.rn.relu.f16x2
331 ; CHECK: fma.rn.ftz.relu.f16x2
339 ; CHECK: fma.rn.bf16
347 ; CHECK: fma.rn.relu.bf16
355 ; CHECK: fma.rn.bf16x2
[all …]
H A Dfma.ll8 ; CHECK: fma.rn.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}};
16 ; CHECK: fma.rn.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}};
17 ; CHECK: fma.rn.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}};
27 ; CHECK: fma.rn.f64 %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}};
35 ; CHECK: fma.rn.f64 %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}};
36 ; CHECK: fma.rn.f64 %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}};
H A Dfma-assoc.ll8 ; CHECK-UNSAFE: fma.rn.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}};
9 ; CHECK-UNSAFE: fma.rn.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}};
20 ; CHECK-UNSAFE: fma.rn.f64 %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}};
21 ; CHECK-UNSAFE: fma.rn.f64 %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}};
34 ; CHECK: fma.rn.f64
H A Di1-int-to-fp.ll7 ; CHECK: cvt.rn.f32.u32
16 ; CHECK: cvt.rn.f32.s32
25 ; CHECK: cvt.rn.f64.u32
34 ; CHECK: cvt.rn.f64.s32
H A Df16-instructions.ll174 ; CHECK-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[FR]];
197 ; CHECK-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[RF]];
691 ; CHECK: cvt.rn.f16.u32 [[R:%h[0-9]+]], [[A]];
701 ; CHECK: cvt.rn.f16.u64 [[R:%h[0-9]+]], [[A]];
711 ; CHECK: cvt.rn.f16.s32 [[R:%h[0-9]+]], [[A]];
721 ; CHECK: cvt.rn.f16.s64 [[R:%h[0-9]+]], [[A]];
731 ; CHECK-DAG: cvt.rn.f16.u32 [[C:%h[0-9]+]], [[A]];
749 ; CHECK-DAG: cvt.rn.f16.s32 [[C:%h[0-9]+]], [[A]];
767 ; CHECK: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[A]];
777 ; CHECK: cvt.rn.f16.f64 [[R:%h[0-9]+]], [[A]];
[all …]
H A Df16x2-instructions.ll231 ; CHECK-DAG: cvt.rn.f16.f32 [[R0:%h[0-9]+]], [[FR0]];
232 ; CHECK-DAG: cvt.rn.f16.f32 [[R1:%h[0-9]+]], [[FR1]];
264 ; CHECK-DAG: cvt.rn.f16.f32 [[R0:%h[0-9]+]], [[RF0]];
265 ; CHECK-DAG: cvt.rn.f16.f32 [[R1:%h[0-9]+]], [[RF1]];
844 ; CHECK-DAG: cvt.rn.f16.u32 [[R0:%h[0-9]+]], [[A0]];
845 ; CHECK-DAG: cvt.rn.f16.u32 [[R1:%h[0-9]+]], [[A1]];
856 ; CHECK-DAG: cvt.rn.f16.u64 [[R0:%h[0-9]+]], [[A0]];
857 ; CHECK-DAG: cvt.rn.f16.u64 [[R1:%h[0-9]+]], [[A1]];
868 ; CHECK-DAG: cvt.rn.f16.s32 [[R0:%h[0-9]+]], [[A0]];
869 ; CHECK-DAG: cvt.rn.f16.s32 [[R1:%h[0-9]+]], [[A1]];
[all …]
H A Dmath-intrins-sm80-ptx70-instcombine.ll28 declare half @llvm.nvvm.fma.rn.f16(half, half, half)
29 declare half @llvm.nvvm.fma.rn.ftz.f16(half, half, half)
275 ; CHECK-NOT: @llvm.nvvm.fma.rn.f16
277 %res = call half @llvm.nvvm.fma.rn.f16(half %0, half %1, half %2)
284 ; CHECK: @llvm.nvvm.fma.rn.ftz.f16
285 %res = call half @llvm.nvvm.fma.rn.ftz.f16(half %0, half %1, half %2)
291 ; CHECK-NOT: @llvm.nvvm.fma.rn.ftz.f16
293 %res = call half @llvm.nvvm.fma.rn.ftz.f16(half %0, half %1, half %2)
299 ; CHECK-NOT: @llvm.nvvm.fma.rn.f16x2
307 ; CHECK-NOT: @llvm.nvvm.fma.rn.ftz.f16x2
[all …]
/llvm-project-15.0.7/llvm/test/MC/X86/
H A Davx512fp16.s469 vcvtdq2ph {rn-sae}, %zmm29, %ymm30
493 vcvtpd2ph {rn-sae}, %zmm29, %xmm30
517 vcvtph2dq {rn-sae}, %ymm29, %zmm30
589 vcvtph2qq {rn-sae}, %xmm29, %zmm30
685 vcvtph2w {rn-sae}, %zmm29, %zmm30
805 vcvtsh2si {rn-sae}, %xmm30, %edx
813 vcvtsh2si {rn-sae}, %xmm30, %r12
877 vcvtsh2usi {rn-sae}, %xmm30, %edx
885 vcvtsh2usi {rn-sae}, %xmm30, %r12
1341 vcvtw2ph {rn-sae}, %zmm29, %zmm30
[all …]
H A Dintel-syntax-avx512fp16.s85 vaddph zmm6, zmm5, zmm4, {rn-sae}
109 vaddsh xmm6, xmm5, xmm4, {rn-sae}
469 vcvtdq2ph ymm6, zmm5, {rn-sae}
493 vcvtpd2ph xmm6, zmm5, {rn-sae}
517 vcvtph2dq zmm6, ymm5, {rn-sae}
589 vcvtph2qq zmm6, xmm5, {rn-sae}
661 vcvtph2uw zmm6, zmm5, {rn-sae}
685 vcvtph2w zmm6, zmm5, {rn-sae}
805 vcvtsh2si edx, xmm6, {rn-sae}
1213 vcvtw2ph zmm6, zmm5, {rn-sae}
[all …]
H A DAVX512F_SCALAR-64.s981 vcvtsd2si {rn-sae}, %xmm15, %r13d
985 vcvtsd2si {rn-sae}, %xmm15, %r15
989 vcvtsd2si {rn-sae}, %xmm1, %r13d
993 vcvtsd2si {rn-sae}, %xmm1, %r15
1377 vcvtsd2usi {rn-sae}, %xmm15, %r15
1381 vcvtsd2usi {rn-sae}, %xmm1, %r13d
1385 vcvtsd2usi {rn-sae}, %xmm1, %r15
2017 vcvtss2si {rn-sae}, %xmm15, %r15
2021 vcvtss2si {rn-sae}, %xmm1, %r13d
2025 vcvtss2si {rn-sae}, %xmm1, %r15
[all …]
H A Davx512fp16-complex-fma.s11 vfcmaddcph {rn-sae}, %zmm24, %zmm23, %zmm23
51 vfcmaddcsh {rn-sae}, %xmm24, %xmm23, %xmm23
91 vfcmulcph {rn-sae}, %zmm24, %zmm23, %zmm23
131 vfcmulcsh {rn-sae}, %xmm24, %xmm23, %xmm23
171 vfmaddcph {rn-sae}, %zmm24, %zmm23, %zmm23
211 vfmaddcsh {rn-sae}, %xmm24, %xmm23, %xmm23
251 vfmulcph {rn-sae}, %zmm24, %zmm23, %zmm23
291 vfmulcsh {rn-sae}, %xmm24, %xmm23, %xmm23
H A Dintel-syntax-avx512-error.s4 vfmsub213ps zmm8{rn-sae} {k2}, zmm8, zmm8
6 vfmsub213ps zmm8{k2} {rn-sae}, zmm8, zmm8
8 vfmsub213ps zmm8{rn-sae}, zmm8, zmm8
H A Davx512-err.s7 vfmsub213ps %zmm8, %zmm8, %zmm8{%k2} {rn-sae}
10 vfmsub213ps %zmm8, %zmm8, %zmm8 {rn-sae}
13 cvtsd2sil {rn-sae}, %xmm1, %eax
H A DAVX512F_SCALAR-32.s93 vaddsd {rn-sae}, %xmm1, %xmm1, %xmm1
97 vaddsd {rn-sae}, %xmm1, %xmm1, %xmm1 {%k2}
225 vaddss {rn-sae}, %xmm1, %xmm1, %xmm1
549 vcvtsd2ss {rn-sae}, %xmm1, %xmm1, %xmm1
873 vdivsd {rn-sae}, %xmm1, %xmm1, %xmm1
1005 vdivss {rn-sae}, %xmm1, %xmm1, %xmm1
5533 vmulsd {rn-sae}, %xmm1, %xmm1, %xmm1
5665 vmulss {rn-sae}, %xmm1, %xmm1, %xmm1
6589 vsqrtsd {rn-sae}, %xmm1, %xmm1, %xmm1
6853 vsubsd {rn-sae}, %xmm1, %xmm1, %xmm1
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/NVPTX/
H A Dnvvm-intrins.ll95 ; FTZ: call float @llvm.nvvm.fma.rn.f
302 ; FTZ: call float @llvm.nvvm.add.rn.f
308 ; NOFTZ: call float @llvm.nvvm.add.rn.f
323 ; FTZ: call float @llvm.nvvm.mul.rn.f
329 ; NOFTZ: call float @llvm.nvvm.mul.rn.f
344 ; FTZ: call float @llvm.nvvm.div.rn.f
350 ; NOFTZ: call float @llvm.nvvm.div.rn.f
361 ; FTZ: call float @llvm.nvvm.rcp.rn.f
367 ; NOFTZ: call float @llvm.nvvm.rcp.rn.f
389 ; FTZ: call float @llvm.nvvm.sqrt.rn.f
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/X86/
H A Davx512fp16.txt85 # INTEL: vaddph zmm30, zmm29, zmm28, {rn-sae}
469 # INTEL: vcvtdq2ph ymm30, zmm29, {rn-sae}
493 # INTEL: vcvtpd2ph xmm30, zmm29, {rn-sae}
517 # INTEL: vcvtph2dq zmm30, ymm29, {rn-sae}
589 # INTEL: vcvtph2qq zmm30, xmm29, {rn-sae}
685 # INTEL: vcvtph2w zmm30, zmm29, {rn-sae}
805 # INTEL: vcvtsh2si edx, xmm30, {rn-sae}
813 # INTEL: vcvtsh2si r12, xmm30, {rn-sae}
877 # INTEL: vcvtsh2usi edx, xmm30, {rn-sae}
885 # INTEL: vcvtsh2usi r12, xmm30, {rn-sae}
[all …]
/llvm-project-15.0.7/llvm/test/MC/VE/
H A DCVTWD.s22 # CHECK-INST: cvt.w.d.sx.rn %s11, 7
24 cvt.w.d.sx.rn %s11, 7
46 # CHECK-INST: cvt.w.d.zx.rn %s11, 7
48 cvt.w.d.zx.rn %s11, 7
H A DCVTWS.s22 # CHECK-INST: cvt.w.s.sx.rn %s11, 7
24 cvt.w.s.sx.rn %s11, 7
46 # CHECK-INST: cvt.w.s.zx.rn %s11, 7
48 cvt.w.s.zx.rn %s11, 7
/llvm-project-15.0.7/llvm/lib/Target/DirectX/
H A DDXIL.td62 string fn_attr = ""; // attribute shorthands: rn=does not access
93 "half;float;", "rn",
103 "i16;i32;i64;", "rn",
113 …ThreadId :dxil_op< "ThreadId", 93, ThreadIdClass, ComputeID, "reads the thread ID", "i32;", "rn",
121 …dxil_op< "GroupId", 94, GroupIdClass, ComputeID, "reads the group ID (SV_GroupID)", "i32;", "rn",
130 "reads the thread ID within the group (SV_GroupThreadID)", "i32;", "rn",
139 …provides a flattened index for a given thread within a given group (SV_GroupIndex)", "i32;", "rn",

12345