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/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Drv32a-valid.s20 lr.w.rl t2, (t3)
33 sc.w.rl t4, t3, (t2)
96 amoswap.w.rl a4, ra, (s0)
99 amoadd.w.rl a1, a2, (a3)
102 amoxor.w.rl a2, a3, (a4)
105 amoand.w.rl a3, a4, (a5)
108 amoor.w.rl a4, a5, (a6)
111 amomin.w.rl a5, a6, (a7)
114 amomax.w.rl s7, s6, (s5)
117 amominu.w.rl s6, s5, (s4)
[all …]
H A Drv64a-valid.s21 lr.d.rl t2, (t3)
38 sc.d.rl t4, t3, (t2)
122 amoswap.d.rl a4, ra, (s0)
126 amoadd.d.rl a1, a2, (a3)
130 amoxor.d.rl a2, a3, (a4)
134 amoand.d.rl a3, a4, (a5)
138 amoor.d.rl a4, a5, (a6)
142 amomin.d.rl a5, a6, (a7)
146 amomax.d.rl s7, s6, (s5)
150 amominu.d.rl s6, s5, (s4)
[all …]
H A Drv64a-invalid.s9 # Only .aq, .rl, and .aqrl suffixes are valid
11 amoor.d.aq.rl a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
H A Drv32a-invalid.s9 # Only .aq, .rl, and .aqrl suffixes are valid
11 amoor.w.aq.rl a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
/llvm-project-15.0.7/clang/test/CodeGen/
H A Darm-atomics-m.c30 long long rl; in test_presence() local
31 __atomic_load(&l, &rl, memory_order_seq_cst); in test_presence()
33 rl = 0; in test_presence()
34 __atomic_store(&l, &rl, memory_order_seq_cst); in test_presence()
H A Darm-atomics-m0.c30 long long rl; in test_presence() local
31 __atomic_load(&l, &rl, memory_order_seq_cst); in test_presence()
33 rl = 0; in test_presence()
34 __atomic_store(&l, &rl, memory_order_seq_cst); in test_presence()
H A Darm-atomics.c32 long long rl; in test_presence() local
33 __atomic_load(&l, &rl, memory_order_seq_cst); in test_presence()
35 rl = 0; in test_presence()
36 __atomic_store(&l, &rl, memory_order_seq_cst); in test_presence()
H A Darm-asm-variable.c9 register uint32_t rl asm("r1"); in foo()
17 : [_rl] "=&r" (rl), [_rh] "=&r" (rh) \ in foo()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMips16InstrInfo.td466 // $op2 $rl, $rr ;test registers rl,rr
1038 // Purpose: b = Cmp rl, rr.
1046 // Purpose: b = Cmpi rl, imm.
1054 // Purpose: b = Slt rl, rr.
1062 // Purpose: b = Slti rl, imm.
1070 // Purpose: b = Sltu rl, rr.
1093 // Purpose: b = Cmp rl, rr.
1101 // Purpose: b = Cmpi rl, imm.
1109 // Purpose: b = Slt rl, rr.
1117 // Purpose: b = Slti rl, imm.
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dppc440-fp-basic.ll15 %mul.rl = fmul double %a.real, %b.real
17 %mul.r = fsub double %mul.rl, %mul.rr
H A Da2-fp-basic.ll15 %mul.rl = fmul double %a.real, %b.real
17 %mul.r = fsub double %mul.rl, %mul.rr
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoA.td19 class LR_r<bit aq, bit rl, bits<3> funct3, string opcodestr>
20 : RVInstRAtomic<0b00010, aq, rl, funct3, OPC_AMO,
29 def _RL : LR_r<0, 1, funct3, opcodestr # ".rl">;
34 class AMO_rr<bits<5> funct5, bit aq, bit rl, bits<3> funct3, string opcodestr>
35 : RVInstRAtomic<funct5, aq, rl, funct3, OPC_AMO,
42 def _RL : AMO_rr<funct5, 0, 1, funct3, opcodestr # ".rl">;
H A DRISCVInstrFormats.td302 class RVInstRAtomic<bits<5> funct5, bit aq, bit rl, bits<3> funct3,
312 let Inst{25} = rl;
/llvm-project-15.0.7/compiler-rt/lib/sanitizer_common/
H A Dsanitizer_linux_libcdep.cpp110 struct rlimit rl; in GetThreadStackTopAndBottom() local
111 CHECK_EQ(getrlimit(RLIMIT_STACK, &rl), 0); in GetThreadStackTopAndBottom()
122 if ((uptr)&rl < segment.end) break; in GetThreadStackTopAndBottom()
125 CHECK((uptr)&rl >= segment.start && (uptr)&rl < segment.end); in GetThreadStackTopAndBottom()
129 uptr stacksize = rl.rlim_cur; in GetThreadStackTopAndBottom()
H A Dsanitizer_mac.cpp420 struct rlimit rl; in GetThreadStackTopAndBottom() local
421 CHECK_EQ(getrlimit(RLIMIT_STACK, &rl), 0); in GetThreadStackTopAndBottom()
423 if (rl.rlim_cur < kMaxThreadStackSize) { in GetThreadStackTopAndBottom()
424 stacksize = rl.rlim_cur; in GetThreadStackTopAndBottom()
H A Dsanitizer_symbolizer_report.cpp250 ScopedErrorReportLock rl; in HandleDeadlySignal() local
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dint-cmp-38.ll48 ; CHECK: c{{l?}}rl %r2, g
66 ; CHECK: c{{l?}}rl %r2, g
/llvm-project-15.0.7/lldb/test/Shell/SymbolFile/NativePDB/Inputs/
H A Dfunction-types-builtins.lldbinit43 dv rl
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/msa/
H A Dfexuprl.ll3 ; Test that fexup[rl].w don't crash LLVM during type legalization.
/llvm-project-15.0.7/lldb/test/Shell/SymbolFile/NativePDB/
H A Dfunction-types-builtins.cpp148 auto rl = &unaryret<long, 11>; variable
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Datomic-cmpxchg.ll271 ; RV32IA-NEXT: sc.w.rl a5, a5, (a3)
307 ; RV64IA-NEXT: sc.w.rl a5, a5, (a3)
347 ; RV32IA-NEXT: sc.w.rl a5, a5, (a3)
383 ; RV64IA-NEXT: sc.w.rl a5, a5, (a3)
423 ; RV32IA-NEXT: sc.w.rl a5, a5, (a3)
459 ; RV64IA-NEXT: sc.w.rl a5, a5, (a3)
499 ; RV32IA-NEXT: sc.w.rl a5, a5, (a3)
535 ; RV64IA-NEXT: sc.w.rl a5, a5, (a3)
1038 ; RV32IA-NEXT: sc.w.rl a4, a4, (a3)
1075 ; RV64IA-NEXT: sc.w.rl a4, a4, (a3)
[all …]
H A Datomic-rmw.ll164 ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
194 ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
228 ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
258 ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
484 ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
514 ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
548 ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
578 ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
804 ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
834 ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
[all …]
/llvm-project-15.0.7/polly/lib/External/isl/imath/
H A Dgmp_compat.c636 unsigned long rl; in GMPZAPI() local
645 CHECK(mp_int_to_uint(r, &rl)); in GMPZAPI()
651 return rl; in GMPZAPI()
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Daccess-non-generic.ll71 ; PTX: ld.shared.f32 %f{{[0-9]+}}, [%{{(r|rl|rd)[0-9]+}}];
74 ; PTX: st.shared.f32 [%{{(r|rl|rd)[0-9]+}}], %f{{[0-9]+}};
/llvm-project-15.0.7/libc/AOR_v20.02/math/test/rtest/
H A Ddotest.c114 static void set_mpc_d(mpc_t z, uint32 rh, uint32 rl, uint32 ih, uint32 il) in set_mpc_d() argument
119 set_mpfr_d(x, rh, rl); in set_mpc_d()
257 uint32 *rh, uint32 *rl, uint32 *rextra, in get_mpc_d() argument
265 get_mpfr_d(x, rh, rl, rextra); in get_mpc_d()

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