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Searched refs:rev8 (Results 1 – 23 of 23) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dbitreverse-shift.ll19 ; RV32ZBKB-NEXT: rev8 a0, a0
22 ; RV32ZBKB-NEXT: rev8 a0, a0
29 ; RV64ZBKB-NEXT: rev8 a0, a0
32 ; RV64ZBKB-NEXT: rev8 a0, a0
45 ; RV32ZBKB-NEXT: rev8 a0, a0
48 ; RV32ZBKB-NEXT: rev8 a0, a0
55 ; RV64ZBKB-NEXT: rev8 a0, a0
58 ; RV64ZBKB-NEXT: rev8 a0, a0
71 ; RV32ZBKB-NEXT: rev8 a0, a0
74 ; RV32ZBKB-NEXT: rev8 a0, a0
[all …]
H A Dbswap-shift.ll22 ; RV32ZB-NEXT: rev8 a0, a0
24 ; RV32ZB-NEXT: rev8 a0, a0
30 ; RV64ZB-NEXT: rev8 a0, a0
32 ; RV64ZB-NEXT: rev8 a0, a0
125 ; RV32ZB-NEXT: rev8 a0, a0
128 ; RV32ZB-NEXT: rev8 a0, a0
134 ; RV64ZB-NEXT: rev8 a0, a0
137 ; RV64ZB-NEXT: rev8 a0, a0
H A Drv64zbkb-intrinsic.ll16 ; Test that rev8 is recognized as preserving zero extension.
33 ; RV64ZBKB-NEXT: rev8 a0, a0
H A Drv32zbkb-intrinsic.ll16 ; Test that rev8 is recognized as preserving zero extension.
33 ; RV32ZBKB-NEXT: rev8 a0, a0
H A Dbswap-bitreverse.ll46 ; RV32ZB-NEXT: rev8 a0, a0
52 ; RV64ZB-NEXT: rev8 a0, a0
58 ; RV32ZBP-NEXT: rev8.h a0, a0
63 ; RV64ZBP-NEXT: rev8.h a0, a0
104 ; RV32ZB-NEXT: rev8 a0, a0
109 ; RV64ZB-NEXT: rev8 a0, a0
115 ; RV32ZBP-NEXT: rev8 a0, a0
187 ; RV32ZB-NEXT: rev8 a2, a1
188 ; RV32ZB-NEXT: rev8 a1, a0
194 ; RV64ZB-NEXT: rev8 a0, a0
[all …]
H A Drv64zbp-intrinsic.ll366 ; RV64ZBP-NEXT: rev8.w a0, a0
380 ; RV64ZBP-NEXT: rev8.w a0, a0
410 ; RV64ZBP-NEXT: rev8.w a0, a0
464 ; RV64ZBP-NEXT: rev8 a0, a0
H A Drv32zbb.ll818 ; RV32ZBB-NEXT: rev8 a0, a0
855 ; RV32ZBB-NEXT: rev8 a2, a1
856 ; RV32ZBB-NEXT: rev8 a1, a0
H A Drv32zbp.ll1873 ; RV32ZBP-NEXT: rev8.h a0, a0
1998 ; RV32ZBP-NEXT: rev8.h a0, a0
1999 ; RV32ZBP-NEXT: rev8.h a1, a1
2450 ; RV32ZBP-NEXT: rev8.h a0, a0
2477 ; RV32ZBP-NEXT: rev8 a0, a0
2514 ; RV32ZBP-NEXT: rev8 a2, a1
2515 ; RV32ZBP-NEXT: rev8 a1, a0
2732 ; RV32ZBP-NEXT: rev8.h a0, a0
2758 ; RV32ZBP-NEXT: rev8.h a0, a0
H A Drv64zbb.ll1047 ; RV64ZBB-NEXT: rev8 a0, a0
1075 ; RV64ZBB-NEXT: rev8 a0, a0
1121 ; RV64ZBB-NEXT: rev8 a0, a0
H A Drv32zbp-intrinsic.ll65 ; RV32ZBP-NEXT: rev8 a0, a0
H A Drv64zbp.ll1790 ; RV64ZBP-NEXT: rev8.h a0, a0
2439 ; RV64ZBP-NEXT: rev8.h a0, a0
2538 ; RV64ZBP-NEXT: rev8 a0, a0
2862 ; RV64ZBP-NEXT: rev8.w a0, a0
2905 ; RV64ZBP-NEXT: rev8.w a0, a0
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Drv32zbb-aliases-valid.s22 # CHECK-S-OBJ-NOALIAS: rev8 t0, t1
23 # CHECK-S-OBJ: rev8 t0, t1
24 rev8 x5, x6 label
H A Drv64zbb-aliases-valid.s22 # CHECK-S-OBJ-NOALIAS: rev8 t0, t1
23 # CHECK-S-OBJ: rev8 t0, t1
24 rev8 x5, x6 label
H A Drv32zbkb-only-valid.s7 # CHECK-ASM-AND-OBJ: rev8 t0, t1
9 rev8 t0, t1 label
H A Drv32zbbp-only-valid.s18 # CHECK-ASM-AND-OBJ: rev8 t0, t1
20 rev8 t0, t1 label
H A Drv64zbkb-valid.s7 # CHECK-ASM-AND-OBJ: rev8 t0, t1
9 rev8 t0, t1 label
H A Drv64zbbp-valid.s30 # CHECK-ASM-AND-OBJ: rev8 t0, t1
32 rev8 t0, t1 label
H A Drv64zbp-aliases-valid.s47 # CHECK-S-OBJ: rev8.h t0, t1
48 rev8.h x5, x6
67 # CHECK-S-OBJ: rev8.w t0, t1
68 rev8.w x5, x6
90 # CHECK-S-OBJ-NOALIAS: rev8 t0, t1
91 # CHECK-S-OBJ: rev8 t0, t1
92 rev8 x5, x6 label
H A Drv32zbp-aliases-valid.s47 # CHECK-S-OBJ: rev8.h t0, t1
48 rev8.h x5, x6
66 # CHECK-S-OBJ-NOALIAS: rev8 t0, t1
67 # CHECK-S-OBJ: rev8 t0, t1
68 rev8 x5, x6 label
H A Drv32zbp-only-valid.s13 # CHECK-OBJ: rev8 t0, t1
H A Drv64zbp-valid.s84 # CHECK-OBJ: rev8 t0, t1
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dbitreverse.ll17 define i8 @rev8(i8 %v) {
18 ; CHECK-LABEL: @rev8(
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZb.td620 // We treat rev8 and orc.b as standalone instructions even though they use a
624 // causes diagnostics to suggest that Zbp rather than Zbb is required for rev8
628 def REV8_RV32 : RVBUnary<0b0110100, 0b11000, 0b101, OPC_OP_IMM, "rev8">,
633 def REV8_RV64 : RVBUnary<0b0110101, 0b11000, 0b101, OPC_OP_IMM, "rev8">,
668 def : InstAlias<"rev8.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01000)>;
701 // rev8 is considered an instruction rather than an alias.
723 def : InstAlias<"rev8.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011000)>;
729 // rev8 is considered an instruction rather than an alias.
946 // We treat rev8 as a separate instruction, so match it directly.
951 // We treat rev8 as a separate instruction, so match it directly.