Searched refs:rets (Results 1 – 5 of 5) sorted by relevance
| /llvm-project-15.0.7/flang/lib/Optimizer/Transforms/ |
| H A D | MemoryAllocation.cpp | 106 llvm::ArrayRef<mlir::Operation *> rets) in AllocaOpConversion() argument 107 : OpRewritePattern(ctx), returnOps(rets) {} in AllocaOpConversion()
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| /llvm-project-15.0.7/llvm/test/CodeGen/Mips/Fast-ISel/ |
| H A D | retabi.ll | 39 define signext i16 @rets() { 41 ; CHECK-LABEL: rets:
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| /llvm-project-15.0.7/llvm/include/llvm/IR/ |
| H A D | IntrinsicsARM.td | 916 multiclass MVEPredicated<list<LLVMType> rets, list<LLVMType> params, 920 def "": Intrinsic<rets, params, props, "", sdprops>; 921 def _predicated: Intrinsic<rets, params # [pred], props, "", sdprops>; 923 multiclass MVEPredicatedM<list<LLVMType> rets, list<LLVMType> params, 926 def "": Intrinsic<rets, params, props>; 927 def _predicated: Intrinsic<rets, params # [pred, 928 !if(!eq(rets[0], llvm_anyvector_ty), 929 LLVMMatchType<0>, rets[0])], props>; 953 multiclass MVEMXPredicated<list<LLVMType> rets, list<LLVMType> flags, 957 def "": Intrinsic<rets, flags # params, props>; [all …]
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| /llvm-project-15.0.7/mlir/include/mlir/IR/ |
| H A D | OpBase.td | 2233 class Results<dag rets> { 2234 dag results = rets;
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| /llvm-project-15.0.7/mlir/test/lib/Dialect/Test/ |
| H A D | TestOps.td | 2908 let results = (outs Variadic<AnyType>:$rets);
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