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Searched refs:ret4 (Results 1 – 18 of 18) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dps-shader-arg-count.ll87 %ret4.1 = insertelement <4 x float> %ret4, float %arg16.f, i32 1
88 %ret4.2 = insertelement <4 x float> %ret4.1, float %arg17.f, i32 2
89 %ret4.3 = insertelement <4 x float> %ret4.2, float %arg18.f, i32 3
133 %ret4.1 = insertelement <4 x float> %ret4, float %arg16.f, i32 1
134 %ret4.2 = insertelement <4 x float> %ret4.1, float %arg17.f, i32 2
135 %ret4.3 = insertelement <4 x float> %ret4.2, float %arg18.f, i32 3
182 %ret4.1 = insertelement <4 x float> %ret4, float %extra_arg2, i32 1
241 %ret4.2 = insertelement <4 x float> %ret4.1, float %arg13, i32 1
242 %ret4.3 = insertelement <4 x float> %ret4.2, float %arg14, i32 2
310 %ret4.2 = insertelement <4 x float> %ret4.1, float %arg15.f, i32 2
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dfast-isel-ret.ll35 define signext i16 @ret4(i16 signext %a) nounwind uwtable ssp {
37 ; CHECK: ret4
/llvm-project-15.0.7/libcxx/test/std/input.output/filesystems/class.path/path.member/
H A Dpath.compare.pass.cpp100 int ret4 = normalize_ret(p1.compare(RV)); in test_compare_basic() local
105 assert(ret1 == ret4); in test_compare_basic()
/llvm-project-15.0.7/clang/test/CodeGen/PowerPC/
H A Dppc32-and-aix-struct-return.c80 Four ret4(void) { return (Four){0.4}; } in ret4() function
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dfast-isel-ret.ll51 define signext i16 @ret4(i16 signext %a) nounwind {
53 ; ELF64-LABEL: ret4
H A Dppc64-i128-abi.ll286 ; %ret4 = call i128 @i128_increment_by_val(i128 %tmp2, i128 %tmp2)
/llvm-project-15.0.7/clang/test/SemaCUDA/
H A Dfunction-overload.cu397 HostReturnTy2 ret4 = host_only_function(1.0f); in test_host_device_single_side_overloading() local
410 HostReturnTy2 ret4 = host_only_function(1.0f); in test_host_device_wrong_side_overloading_inline_no_diag() local
423 HostReturnTy2 ret4 = host_only_function(1.0f); in test_host_device_wrong_side_overloading_inline_diag() local
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dbswap-02.ll121 %ret4 = add i32 %ret3, %swapped4
122 %ret5 = add i32 %ret4, %swapped5
H A Dbswap-03.ll121 %ret4 = add i64 %ret3, %swapped4
122 %ret5 = add i64 %ret4, %swapped5
/llvm-project-15.0.7/clang/test/CodeGenOpenCL/
H A Datomics-cas-remarks-gfx90a.cl42 float ret4 = __opencl_atomic_fetch_add(d, a, memory_order_relaxed, memory_scope_sub_group);
/llvm-project-15.0.7/llvm/test/Transforms/Attributor/
H A Dinternalize.ll120 %ret4 = call i32 @inner4(i32 %ret3, i32 %ret3)
121 ret i32 %ret4
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Denvreg.ll111 %ret4 = add i32 %ret3, %val5
112 %ret5 = add i32 %ret4, %val6
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dvar-permute-256.ll126 %ret4 = insertelement <8 x i32> %ret3, i32 %v4, i32 4
127 %ret5 = insertelement <8 x i32> %ret4, i32 %v5, i32 5
250 %ret4 = insertelement <16 x i16> %ret3, i16 %v4, i32 4
251 %ret5 = insertelement <16 x i16> %ret4, i16 %v5, i32 5
403 %ret4 = insertelement <32 x i8> %ret3, i8 %v4, i32 4
404 %ret5 = insertelement <32 x i8> %ret4, i8 %v5, i32 5
546 %ret4 = insertelement <8 x float> %ret3, float %v4, i32 4
796 %ret4 = insertelement <16 x i16> %ret3, i16 %v4, i32 4
797 %ret5 = insertelement <16 x i16> %ret4, i16 %v5, i32 5
947 %ret4 = insertelement <32 x i8> %ret3, i8 %v4, i32 4
[all …]
H A Dvar-permute-128.ll219 %ret4 = insertelement <8 x i16> %ret3, i16 %v4, i32 4
220 %ret5 = insertelement <8 x i16> %ret4, i16 %v5, i32 5
362 %ret4 = insertelement <16 x i8> %ret3, i8 %v4, i32 4
363 %ret5 = insertelement <16 x i8> %ret4, i8 %v5, i32 5
627 %ret4 = insertelement <16 x i8> %ret3, i8 %v4, i32 4
628 %ret5 = insertelement <16 x i8> %ret4, i8 %v5, i32 5
1090 %ret4 = insertelement <16 x i8> %ret3, i8 %v4, i32 4
1091 %ret5 = insertelement <16 x i8> %ret4, i8 %v5, i32 5
H A Dvar-permute-512.ll31 %ret4 = insertelement <8 x i64> %ret3, i64 %v4, i32 4
32 %ret5 = insertelement <8 x i64> %ret4, i64 %v5, i32 5
79 %ret4 = insertelement <16 x i32> %ret3, i32 %v4, i32 4
80 %ret5 = insertelement <16 x i32> %ret4, i32 %v5, i32 5
292 %ret4 = insertelement <32 x i16> %ret3, i16 %v4, i32 4
293 %ret5 = insertelement <32 x i16> %ret4, i16 %v5, i32 5
910 %ret4 = insertelement <64 x i8> %ret3, i8 %v4, i32 4
911 %ret5 = insertelement <64 x i8> %ret4, i8 %v5, i32 5
998 %ret4 = insertelement <8 x double> %ret3, double %v4, i32 4
1046 %ret4 = insertelement <16 x float> %ret3, float %v4, i32 4
[all …]
H A Davx512bw-intrinsics-upgrade.ll1931 %ret4 = add i64 %ret3, %res4
1933 %ret5 = add i64 %ret4, %res5
2017 %ret4 = add i64 %ret3, %res4
2019 %ret5 = add i64 %ret4, %res5
2104 %ret4 = add i64 %ret3, %res4
2106 %ret5 = add i64 %ret4, %res5
2190 %ret4 = add i64 %ret3, %res4
2192 %ret5 = add i64 %ret4, %res5
2254 %ret4 = add i32 %ret3, %res4
2256 %ret5 = add i32 %ret4, %res5
[all …]
/llvm-project-15.0.7/compiler-rt/test/dfsan/
H A Dcustom.cpp1177 int ret4 = inet_pton(AF_INET, addr4, &in4); in test_inet_pton() local
1178 assert(ret4 == 1); in test_inet_pton()
1179 ASSERT_ZERO_LABEL(ret4); in test_inet_pton()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.td58 list<SubRegIndex> ret4 = [sub0, sub1, sub2, sub3];
78 !if(!eq(size, 4), ret4,