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/llvm-project-15.0.7/mlir/include/mlir/Dialect/SPIRV/IR/
H A DSPIRVGLOps.td213 restricted-float-scalar-type |
245 restricted-float-scalar-type |
277 restricted-float-scalar-type |
311 restricted-float-scalar-type |
345 restricted-float-scalar-type |
379 restricted-float-scalar-type |
411 restricted-float-scalar-type |
535 restricted-float-scalar-type |
751 restricted-float-scalar-type |
872 restricted-float-scalar-type |
[all …]
H A DSPIRVCLOps.td378 restricted-float-scalar-type ::= `f16` | `f32`
379 restricted-float-scalar-vector-type ::=
380 restricted-float-scalar-type |
381 `vector<` integer-literal `x` restricted-float-scalar-type `>`
383 restricted-float-scalar-vector-type
/llvm-project-15.0.7/lldb/test/Shell/SymbolFile/Breakpad/
H A Dstack-cfi-parsing.test7 # CHECK: Asynchronous (not restricted to call-sites) UnwindPlan is 'breakpad STACK CFI'
8 # CHECK: Synchronous (restricted to call-sites) UnwindPlan is 'breakpad STACK CFI'
48 # CHECK: Asynchronous (not restricted to call-sites) UnwindPlan is 'breakpad STACK CFI'
49 # CHECK: Synchronous (restricted to call-sites) UnwindPlan is 'breakpad STACK CFI'
H A Dunwind-via-stack-cfi.test9 # CHECK: Asynchronous (not restricted to call-sites) UnwindPlan is 'breakpad STACK CFI'
10 # CHECK: Synchronous (restricted to call-sites) UnwindPlan is 'breakpad STACK CFI'
/llvm-project-15.0.7/lldb/test/Shell/Unwind/
H A Dprefer-debug-over-eh-frame.test21 # CHECK: Asynchronous (not restricted to call-sites) UnwindPlan is 'DWARF CFI plus augmentation fro…
22 # CHECK: Synchronous (restricted to call-sites) UnwindPlan is 'DWARF CFI'
H A Deh-frame-augment-noop.test19 # CHECK: Asynchronous (not restricted to call-sites) UnwindPlan is 'eh_frame CFI'
/llvm-project-15.0.7/mlir/include/mlir/Analysis/Presburger/
H A DSimplex.h239 : pos(oPos), orientation(oOrientation), restricted(oRestricted), in pos()
243 bool restricted : 1; member
249 if (restricted) in print()
/llvm-project-15.0.7/llvm/test/MC/Hexagon/PacketRules/
H A Drestrict_slot1_aok.s7 # CHECK: 5:3: note: Instruction was restricted from being in slot 1
H A Drestrict_no_slot1_store.s13 # CHECK: note: Instruction was restricted from being in slot 1
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DP9InstrResources.td452 // These operations can be done in parallel. The DP is restricted so we need a
826 // Full 6 dispatches are required as this is both cracked and restricted.
847 // Full 6 dispatches are required as this is a restricted instruction.
889 // Single slice Restricted store operation. The restricted operation requires
1020 // Cracked, restricted, ALU operations.
1047 // One of the ALU ops is restricted the other is not so we have a total of
1084 // One of the ALU ops is restricted and takes 3 dispatches.
1099 // Both of the ALU ops are restricted and take 3 dispatches.
1107 // total of 6 cycles. All of the ALU operations are also restricted so each
1251 // also restricted.
[all …]
H A DPPCScheduleP9.td58 // of the superslice, but are restricted to iops with only two primary sources.
/llvm-project-15.0.7/clang-tools-extra/docs/clang-tidy/checks/objc/
H A Dforbidden-subclassing.rst18 See https://clang.llvm.org/docs/AttributeReference.html#objc-subclassing-restricted
/llvm-project-15.0.7/lld/test/ELF/
H A Dreloc-sec-before-relocated.test4 ## want to use this feature, which is not restricted by ELF gABI.
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dmad24-get-global-id.ll3 ; If the workgroup id range is restricted, we should be able to use
H A Dregalloc-fail-unsatisfiable-overlapping-tuple-hints.mir4 # This testcase is restricted to use a maximum of 24 VGPRs. It is
/llvm-project-15.0.7/mlir/test/Pass/
H A Dpipeline-parsing.mlir14 // CHECK_ERROR_5: Can't add pass '{{.*}}TestModulePass' restricted to 'builtin.module' on a PassMa…
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/PowerPC/
H A Dinterleaved-pointer-runtime-check-unprofitable.ll7 ; Interleaving should also be restricted by the threshold of memory checks similar to VF.
/llvm-project-15.0.7/clang/test/Modules/
H A DWerror.m16 // Make the build more restricted (-Werror)
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dv60_sort16.ll2 ; Looking for 3rd register field to be restricted to r0-r7.
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DREADME.txt5 The initial backend is deliberately restricted to z10. We should add support
/llvm-project-15.0.7/llvm/test/Transforms/LoopUnroll/
H A Dpeel-loop-not-forced.ll95 ; us to peel twice because we are restricted to 30 instructions in resulting
/llvm-project-15.0.7/mlir/lib/Analysis/Presburger/
H A DSimplex.cpp863 if (unknownFromColumn(j).restricted && in findPivot()
1015 if (!unknownFromRow(row).restricted) in findPivotRow()
1357 if (u.restricted && direction == Direction::Down && in computeOptimum()
/llvm-project-15.0.7/llvm/docs/HistoricalNotes/
H A D2003-06-25-Reoptimizer1.txt104 We are restricted to using single instructions to branch between the
/llvm-project-15.0.7/lld/test/COFF/Inputs/
H A Dpdb-type-server-guid-collision-b-pdb.yaml243 Name: restricted
H A Dpdb-type-server-guid-collision-a-pdb.yaml215 Name: restricted

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