Searched refs:requiresAccessGroup (Results 1 – 3 of 3) sorted by relevance
| /llvm-project-15.0.7/mlir/tools/mlir-tblgen/ |
| H A D | LLVMIRIntrinsicGen.cpp | 202 bool requiresAccessGroup = in emitIntrinsic() local
219 if (requiresAccessGroup) in emitIntrinsic()
235 << (requiresAccessGroup ? "1" : "0") << ", " in emitIntrinsic()
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| /llvm-project-15.0.7/mlir/include/mlir/Dialect/ArmNeon/ |
| H A D | ArmNeon.td | 43 list<Trait> traits = [], bit requiresAccessGroup = 0,
52 /*requiresAccessGroup=*/requiresAccessGroup,
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| /llvm-project-15.0.7/mlir/include/mlir/Dialect/LLVMIR/ |
| H A D | LLVMOpBase.td | 301 bit requiresAccessGroup = 0, bit requiresAliasScope = 0>
320 }] # !if(!gt(requiresAccessGroup, 0),
333 int numResults, bit requiresAccessGroup = 0,
337 numResults, requiresAccessGroup, requiresAliasScope>;
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