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Searched refs:representation (Results 1 – 25 of 217) sorted by relevance

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/llvm-project-15.0.7/libunwind/src/
H A DUnwind-EHABI.cpp891 switch (representation) { in ValueAsBitPattern()
913 representation, in _Unwind_VRS_Set()
925 if (representation != _UVRSD_VFPX && representation != _UVRSD_DOUBLE) in _Unwind_VRS_Set()
927 if (representation == _UVRSD_VFPX) { in _Unwind_VRS_Set()
988 if (representation != _UVRSD_VFPX && representation != _UVRSD_DOUBLE) in _Unwind_VRS_Get_Internal()
990 if (representation == _UVRSD_VFPX) { in _Unwind_VRS_Get_Internal()
1046 representation, in _Unwind_VRS_Get()
1058 representation); in _Unwind_VRS_Pop()
1065 if (representation != _UVRSD_UINT32) in _Unwind_VRS_Pop()
1097 if (representation != _UVRSD_VFPX && representation != _UVRSD_DOUBLE) in _Unwind_VRS_Pop()
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/llvm-project-15.0.7/clang-tools-extra/docs/clang-tidy/checks/bugprone/
H A Dsuspicious-memory-comparison.rst14 **Case 2: Types with no unique object representation**
16 Objects with the same value may not have the same object representation.
30 …-CPP. Do not access the bits of an object representation that are not part of the object's value r…
31 …CPP.+Do+not+access+the+bits+of+an+object+representation+that+are+not+part+of+the+object%27s+value+…
/llvm-project-15.0.7/libunwind/include/
H A Dunwind_arm_ehabi.h115 uint32_t regno, _Unwind_VRS_DataRepresentation representation,
120 uint32_t regno, _Unwind_VRS_DataRepresentation representation,
126 _Unwind_VRS_DataRepresentation representation);
/llvm-project-15.0.7/lldb/test/Shell/ScriptInterpreter/Python/Crashlog/
H A Dpatch-crashlog.py46 representation = int
48 representation = hex
50 "@{}@".format(symbol), str(representation(patch_addr)))
/llvm-project-15.0.7/polly/
H A DREADME5 Polly uses a mathematical representation, the polyhedral model, to represent and
7 representation it is possible to reason about transformations in a more general
/llvm-project-15.0.7/llvm/docs/HistoricalNotes/
H A D2000-12-06-MeetingSummary.txt4 We met to discuss the LLVM instruction format and bytecode representation:
21 common case and inflate the instruction representation with another
39 representation. This is one example of an analysis result that may be
43 to the order of occurrence in the bytecode representation.
H A D2001-02-13-Reference-Memory.txt24 representation.
33 when we don't want the "pinned" representation. This is not
H A D2001-02-13-Reference-MemoryResponse.txt15 > representation.
37 > when we don't want the "pinned" representation. This is not
/llvm-project-15.0.7/lldb/examples/customization/bin-utils/
H A DREADME23 Convert the integer to print its two's complement representation.
25 args[1] (mandatory) is the bit width of the two's complement representation
/llvm-project-15.0.7/lldb/source/Plugins/TraceExporter/docs/
H A Dhtr.rst11 **Layer:** The representation of trace data between passes. For Intel PT there are two types of lay…
21 …that generates a new *layer* that is a more summarized, consolidated representation of the trace d…
24 The image below illusrates the transformation of a trace's representation (HTR)
31 …to extract useful information (summarization) and compress the trace representation into a new *la…
/llvm-project-15.0.7/mlir/docs/Rationale/
H A DRationaleSimplifiedPolyhedralForm.md24 Our currently planned representation for MLIR consists of two kinds of
45 the first place: though our base "CFG function" representation is fully capable
63 We started by discussing a representation that uses the traditional polyhedral
64 schedule set + domain representation, e.g. consider C-like code like:
78 The polyhedral representation doesn't care about the actual computation, so we
105 SSA values more explicit. This leads us to a representation along the lines of:
127 representation, and makes lexical ordering within a loop significant
130 It isn't obvious in the example above, but the representation allows for some
170 an mlfunc to a cfgfunc representation) handles this power so things that
178 form, we would have a representation where all instructions inside of a given
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H A DRationale.md13 MLIR is a compiler intermediate representation with similarities to traditional
35 sequential computation. The representation allows high-level optimization and
46 representation such as HLO or TensorFlow graphs, all the way down to the machine
49 This is a key distinction from existing polyhedral representation
55 control flow does not preclude representation in MLIR, but only limits to a
60 underlying a polyhedral representation of high-dimensional loop nests and
126 have an SSA representation --
191 is defined away with BB argument representation.
462 This representation was chosen for several reasons:
730 necessary such a domain schedule representation can be normalized to
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/llvm-project-15.0.7/llvm/docs/GlobalISel/
H A Dindex.rst24 representation, which has a compile-time cost.
26 GlobalISel directly operates on the post-isel representation used by the
28 It does require extensions to that representation to support arbitrary
/llvm-project-15.0.7/libcxx/docs/DesignDocs/
H A DFileTimeType.rst39 our own filesystem clock which specifies the period and representation of
58 But what type can we use as the arithmetic representation that is capable
140 64 bit representation requires limiting the resolution to seconds.
146 representation, not design it.
188 As we've discussed, ``file_time_type`` needs a representation that uses more
238 to the particular eccentricities of the representation, hopefully only in such
242 representation we choose. But some representations may be quirkier than others,
279 number of ticks stored using ``rep``. The representation is unaware of the
318 and maximum values for a custom representation. It looks like this:
334 Notice that ``duration_values`` doesn't tell the representation what tick
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/llvm-project-15.0.7/clang/include/clang/Basic/
H A DTargetCXXABI.def39 /// - the representation of member function pointers is adjusted
81 /// - representation of member function pointers adjusted as in ARM.
88 /// - representation of member function pointers adjusted as in ARM.
94 /// - representation of member function pointers is adjusted, as in ARM;
/llvm-project-15.0.7/llvm/docs/
H A DFAQ.rst43 What API do I use to store a value to one of the virtual registers in LLVM IR's SSA representation?
58 Longer explanation: In order to generate a textual representation of the
61 representation that you manipulate from C++ has no such restriction since
64 not explicitly represented in the in-memory representation at all (see
83 LLVM intermediate representation (IR) format. Assuming you want to write your
126 Currently, there isn't much. LLVM supports an intermediate representation
127 which is useful for code representation but will not support the high level
128 (abstract syntax tree) representation needed by most compilers. There are no
H A DBlockFrequencyTerminology.rst42 and this simple graph representation::
51 representation.
76 fixed-point representation where ``UINT64_MAX`` represents ``1.0`` and ``0``
/llvm-project-15.0.7/mlir/lib/IR/
H A DPatternMatch.cpp18 PatternBenefit::PatternBenefit(unsigned benefit) : representation(benefit) { in PatternBenefit()
19 assert(representation == benefit && benefit != ImpossibleToMatchSentinel && in PatternBenefit()
25 return representation; in getBenefit()
/llvm-project-15.0.7/clang/docs/
H A DPCHInternals.rst26 representation after it has completed parsing and semantic analysis. The PCH
68 Clang's AST files are designed with a compact on-disk representation, which
70 file. The AST file itself contains a serialized representation of Clang's
135 which contains the serialized representation of a part of Clang's internal
136 representation. Each of the blocks corresponds to either a block or a record
204 The source manager block contains the serialized representation of Clang's
232 The preprocessor block contains the serialized representation of the
245 The types block contains the serialized representation of all of the types
257 the types block where the serialized representation of that type resides,
268 The declarations block contains the serialized representation of all of the
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/llvm-project-15.0.7/llvm/test/Bitcode/
H A DDICompileUnit-no-DWOId.ll2 ; default to 0, which is not displayed at all in the textual representation.
H A Dmetadata-source.ll1 ; Test that DIFile representation upgrades with introduction of
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AArch64/
H A Da64-ignored-fields.txt4 # The "Rm" bits are ignored, but the canonical representation has them filled
/llvm-project-15.0.7/llvm/bindings/ocaml/bitwriter/
H A Dllvm_bitwriter.ml10 * representation, the classes in the VMCore library.
/llvm-project-15.0.7/compiler-rt/lib/builtins/
H A Dfp_compare_impl.inc70 // complement integer representation; if integers are represented in a
71 // sign-magnitude representation, then this flip is incorrect).
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Dpow2_mask_cmp.ll10 ; value will be identical regardless of the boolean representation.

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