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Searched refs:regclass (Results 1 – 24 of 24) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.td2515 (outs regclass:$dst1, regclass:$dst2, regclass:$dst3, regclass:$dst4),
2521 (outs regclass:$dst1, regclass:$dst2, regclass:$dst3, regclass:$dst4),
2527 (outs regclass:$dst1, regclass:$dst2, regclass:$dst3, regclass:$dst4),
2533 (outs regclass:$dst1, regclass:$dst2, regclass:$dst3, regclass:$dst4),
2539 (outs regclass:$dst1, regclass:$dst2, regclass:$dst3, regclass:$dst4),
2604 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2611 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2618 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2625 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2632 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
[all …]
H A DNVPTXIntrinsics.td1481 [(set regclass:$dst, (IntOp ptrclass:$addr, regclass:$b, regclass:$c))]>,
2166 def _areg32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2169 def _areg64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2172 def _ari32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2175 def _ari64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2178 def _avar: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2287 def _areg32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2290 def _areg64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2293 def _ari32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2296 def _ari64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
[all …]
/llvm-project-15.0.7/libunwind/src/
H A DUnwind-EHABI.cpp907 _Unwind_VRS_Set(_Unwind_Context *context, _Unwind_VRS_RegClass regclass, in _Unwind_VRS_Set() argument
912 static_cast<void *>(context), regclass, regno, in _Unwind_VRS_Set()
916 switch (regclass) { in _Unwind_VRS_Set()
975 _Unwind_VRS_RegClass regclass, uint32_t regno, in _Unwind_VRS_Get_Internal() argument
979 switch (regclass) { in _Unwind_VRS_Get_Internal()
1037 _Unwind_VRS_Get(_Unwind_Context *context, _Unwind_VRS_RegClass regclass, in _Unwind_VRS_Get() argument
1041 _Unwind_VRS_Get_Internal(context, regclass, regno, representation, in _Unwind_VRS_Get()
1045 static_cast<void *>(context), regclass, regno, in _Unwind_VRS_Get()
1059 switch (regclass) { in _Unwind_VRS_Pop()
1079 if (regclass == _UVRSC_CORE && i == 13) in _Unwind_VRS_Pop()
[all …]
/llvm-project-15.0.7/libunwind/include/
H A Dunwind_arm_ehabi.h114 _Unwind_VRS_Get(_Unwind_Context *context, _Unwind_VRS_RegClass regclass,
119 _Unwind_VRS_Set(_Unwind_Context *context, _Unwind_VRS_RegClass regclass,
124 _Unwind_VRS_Pop(_Unwind_Context *context, _Unwind_VRS_RegClass regclass,
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dgreedy-liverange-priority.mir1 # RUN: llc -march=amdgcn -mcpu=gfx1030 -greedy-regclass-priority-trumps-globalness=0 -start-before …
2 # RUN: llc -march=amdgcn -mcpu=gfx1030 -greedy-regclass-priority-trumps-globalness=1 -start-before …
4 # At the time of writing -greedy-regclass-priority-trumps-globalness makes a
H A Dsgpr-copy.ll210 ; registers were being identified as an SGPR regclass which was causing
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dvariable_elem_vec_extracts.ll100 ; FIXME: the instruction below is a redundant regclass copy, to be removed
106 ; FIXME: the instruction below is a redundant regclass copy, to be removed
112 ; FIXME: the instruction below is a redundant regclass copy, to be removed
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrCDE.td471 class CDE_VCX_RegisterOperandsTemplate<RegisterClass regclass>
473 let Rd = (outs regclass:$Vd);
474 let Rd_src = (ins regclass:$Vd_src);
475 let Rn = (ins regclass:$Vn);
476 let Rm = (ins regclass:$Vm);
479 class CDE_VCXQ_RegisterOperandsTemplate<RegisterClass regclass>
481 let Rd = (outs regclass:$Qd);
482 let Rd_src = (ins regclass:$Qd_src);
483 let Rn = (ins regclass:$Qn);
484 let Rm = (ins regclass:$Qm);
H A DARMInstrThumb2.td1504 // can be SP. We need another regclass (similar to rGPR) to represent
H A DARMInstrInfo.td2534 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dlocalizer.mir90 ; The newly created reg should be on the same regbank/regclass as its origin.
117 ; The newly created reg should be on the same regbank/regclass as its origin.
148 ; The newly created reg should be on the same regbank/regclass as its origin.
184 ; The newly created reg should be on the same regbank/regclass as its origin.
220 ; The newly created reg should be on the same regbank/regclass as its origin.
256 ; The newly created reg should be on the same regbank/regclass as its origin.
293 ; The newly created reg should be on the same regbank/regclass as its origin.
330 ; The newly created reg should be on the same regbank/regclass as its origin.
H A Drbs-matrixindex-regclass-crash.mir4 # Check we don't crash because of an unhandled new regclass GPR64_with_sub_32_in_MatrixIndexGPR32_1…
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dcoalescer-subreg.ll2 ; This used to crash when coalescing a regclass like GR16 which did not support
H A Dh-registers-0.ll38 ; See FIXME: on regclass GR8.
/llvm-project-15.0.7/llvm/test/TableGen/
H A Dbare-minimum-psets.td5 // Allowed the pset only for D_32 regclass and ignored it for all
H A DGlobalISelEmitter.td1010 //===- Test a simple pattern with regclass operands. ----------------------===//
1081 //===- Test another simple pattern with regclass operands. ----------------===//
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dearly-ifcvt-regclass-mismatch.mir116 ; some operands to the PHI have the fpr64 regclass.
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dvldlane.ll933 ; in the QPR_VFP2 regclass, it needs to be copied to a QPR regclass because
934 ; we don't currently have a QQQQ_VFP2 super-regclass. (The "0" for the low
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrArithmetic.td539 class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
554 RegisterClass RegClass = regclass;
657 // both a regclass and EFLAGS as a result.
665 // both a regclass and EFLAGS as a result, and has EFLAGS as input.
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTarget.td794 /// type that it doesn't know, and resolves the actual regclass to use by using
907 class RegisterOperand<RegisterClass regclass, string pm = "printOperand">
910 RegisterClass RegClass = regclass;
1172 let InOperandList = (ins unknown:$src, i32imm:$regclass);
/llvm-project-15.0.7/llvm/include/llvm/Support/
H A DTargetOpcodes.def101 // pair. Once it has been lowered to a MachineInstr, the regclass operand
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVPseudos.td74 class LMULInfo<int lmul, int oct, VReg regclass, VReg wregclass,
77 VReg vrclass = regclass;
122 class FPR_Info<RegisterClass regclass, string fx, list<LMULInfo> mxlist> {
123 RegisterClass fprclass = regclass;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td248 // Condition code regclass.
H A DAArch64InstrFormats.td989 class arith_shifted_reg<ValueType Ty, RegisterClass regclass, int width>
993 let MIOperandInfo = (ops regclass, !cast<Operand>("arith_shift" # width));
1019 class logical_shifted_reg<ValueType Ty, RegisterClass regclass, Operand shiftop>
1023 let MIOperandInfo = (ops regclass, shiftop);